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Pull requests: OpenXiangShan/XiangShan

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Pull requests list

feat(Config, DCacheWrapper): Transfer PC to L2 via TL to support L2 Nextline prefetcher. module: memory Memblock, DCache, TLB, Prefetcher, coupledL2, huancun module: top XSTop, XSTile, XSParameters, configs note: submodule bump (PR) For maintainer: this bumps submodule, merge carefully topic: functionality To introduce new function, e.g. new isa extensions, new components, bug fixes...
#5793 opened Apr 9, 2026 by zzQGyy Loading…
1
fix(Fence): upper two bits of VMID must be zero in hardware module: backend Decode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuan
#5788 opened Apr 8, 2026 by good-circle Contributor Loading…
11
fix(backend, ctrlblock): export empty state to ftq when backend drains module: backend Decode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuan module: frontend Bpu, Ftq, Ifu, ICache, IBuffer topic: functionality To introduce new function, e.g. new isa extensions, new components, bug fixes...
#5787 opened Apr 8, 2026 by wissygh Contributor • Draft
1
refactor(SBuffer): remove unused signals and functions and reduce logic module: memory Memblock, DCache, TLB, Prefetcher, coupledL2, huancun module: tool non-RTL tools like difftest, gsim, XSpdb, Makefiles, scripts, CI/CD, etc. note: submodule bump (PR) For maintainer: this bumps submodule, merge carefully
#5785 opened Apr 8, 2026 by skyhgzsh Contributor Loading…
8
power(tage): separate tage write ctr and write useful module: frontend Bpu, Ftq, Ifu, ICache, IBuffer topic: power To reduce power consumption
#5782 opened Apr 8, 2026 by out-of-order55 Contributor Loading… kmh-v3
6
feat(missQueue, sbuffer): sbuffer releases the entry when miss accepted by mshr, and mshr provides st-ld forwarding module: memory Memblock, DCache, TLB, Prefetcher, coupledL2, huancun
#5778 opened Apr 7, 2026 by jlong299 Contributor Loading…
1
feat(abtb): adjust abtb indexing and replacement strategy module: frontend Bpu, Ftq, Ifu, ICache, IBuffer
#5776 opened Apr 7, 2026 by my-mayfly Collaborator • Draft
5
feat(ICache): 2-prefetch module: frontend Bpu, Ftq, Ifu, ICache, IBuffer topic: functionality To introduce new function, e.g. new isa extensions, new components, bug fixes...
#5775 opened Apr 7, 2026 by ngc7331 Member • Draft
3
area(tage): use SRAM to store usefulCtr module: frontend Bpu, Ftq, Ifu, ICache, IBuffer topic: area To reduce area comsuption
#5774 opened Apr 7, 2026 by TheKiteRunner24 Collaborator • Draft
fix(VLSU): fix vec misalign stuck module: memory Memblock, DCache, TLB, Prefetcher, coupledL2, huancun
#5771 opened Apr 6, 2026 by Anzooooo Member • Draft
Just run CI for test module: memory Memblock, DCache, TLB, Prefetcher, coupledL2, huancun
#5764 opened Apr 3, 2026 by jlong299 Contributor Loading…
1
feat(missQueue, sbuffer): sbuffer releases the entry when miss accepted by mshr, and mshr provides st-ld forwarding module: memory Memblock, DCache, TLB, Prefetcher, coupledL2, huancun
#5761 opened Apr 3, 2026 by jlong299 Contributor Loading…
1
refactor: new StoreUnit module: backend Decode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuan module: memory Memblock, DCache, TLB, Prefetcher, coupledL2, huancun module: other ChiselAIA, IMSIC, CLINT, etc. module: top XSTop, XSTile, XSParameters, configs
#5760 opened Apr 2, 2026 by ywlcode Contributor Loading…
5
feat(ftq): drop resolve when no mispredict module: frontend Bpu, Ftq, Ifu, ICache, IBuffer topic: functionality To introduce new function, e.g. new isa extensions, new components, bug fixes...
#5759 opened Apr 2, 2026 by TheKiteRunner24 Collaborator Loading…
12
fix(config): fix KunminghuV2MinimalConfig module: top XSTop, XSTile, XSParameters, configs topic: functionality To introduce new function, e.g. new isa extensions, new components, bug fixes...
#5758 opened Apr 2, 2026 by xiaokamikami Member Loading…
fix(Rob): vsetvl zero, zero should not respond to interrupts module: backend Decode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuan
#5757 opened Apr 2, 2026 by Anzooooo Member Loading…
feat(missQueue, sbuffer): sbuffer releases the entry when miss accepted by mshr, and mshr provides st-ld forwarding module: memory Memblock, DCache, TLB, Prefetcher, coupledL2, huancun
#5755 opened Apr 2, 2026 by jlong299 Contributor Loading…
1
fix(LoadUnit): rfWen should be false when an exception occurs module: memory Memblock, DCache, TLB, Prefetcher, coupledL2, huancun
#5750 opened Mar 31, 2026 by good-circle Contributor Loading…
feat(csr): Add inline CSR docs and CSV dump export module: backend Decode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuan module: tool non-RTL tools like difftest, gsim, XSpdb, Makefiles, scripts, CI/CD, etc. module: top XSTop, XSTile, XSParameters, configs topic: functionality To introduce new function, e.g. new isa extensions, new components, bug fixes...
#5749 opened Mar 31, 2026 by poemonsense Member Loading…
3
feat(dispatch): increase load IQ's numEnq from 2 to 3 module: backend Decode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuan module: top XSTop, XSTile, XSParameters, configs
#5747 opened Mar 31, 2026 by xiaofeibao-xjtu Contributor • Draft
refactor(exception): use sparse vector (SparseVec) for exception vector module: backend Decode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuan module: frontend Bpu, Ftq, Ifu, ICache, IBuffer module: memory Memblock, DCache, TLB, Prefetcher, coupledL2, huancun module: top XSTop, XSTile, XSParameters, configs topic: code quality To make code more readable & maintainable
#5738 opened Mar 29, 2026 by Squareless-XD Member Loading…
3
perf(stream): enable decr mode module: memory Memblock, DCache, TLB, Prefetcher, coupledL2, huancun topic: functionality To introduce new function, e.g. new isa extensions, new components, bug fixes...
#5737 opened Mar 28, 2026 by Maxpicca-Li Member • Draft
1
timing(bpu): use sram.resetDone instead of r.req.ready module: frontend Bpu, Ftq, Ifu, ICache, IBuffer topic: timing To fix bad timing
#5735 opened Mar 27, 2026 by ngc7331 Member Loading…
6
timing(ICache): move parity check to s2 module: frontend Bpu, Ftq, Ifu, ICache, IBuffer topic: timing To fix bad timing
#5733 opened Mar 27, 2026 by ngc7331 Member • Draft
2
20260326 release new module: memory Memblock, DCache, TLB, Prefetcher, coupledL2, huancun module: top XSTop, XSTile, XSParameters, configs
#5729 opened Mar 26, 2026 by good-circle Contributor • Draft
ProTip! Updated in the last three days: updated:>2026-04-06.