fix(Fence): upper two bits of VMID must be zero in hardware

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[fuhuakai]

The direction of this fix is correct, but it introduces new timing issues. sfence.bits.id is sampled in the same cycle as io.in.fire via RegEnable, but useVmid comes from the registered func, which is the type of the previous uop rather than the type of the current input instruction, causing a timing misalignment.
Let's assume that at cycle t-1, io.in.bits is a hfence_g instruction, while at cycle t, io.in.bits is not a hfence_g instruction. In this case, useVmid will be incorrectly set to 1 at cycle t, causing sfence.bits.id to erroneously use fenceVmid (when it should actually be fenceAsid).
A very simple fix is to change:
val useVmid = func === FenceOpType.hfence_g
to
val useVmid = io.in.bits.ctrl.fuOpType === FenceOpType.hfence_g