[Kernel] Add enable_sm120_or_later for SM121 (DGX Spark) CUTLASS support

[Code4me2]

Summary

Add enable_sm120_or_later kernel wrapper to support SM121 (DGX Spark GB10) in addition to SM120 (RTX 5090) for Blackwell CUTLASS kernels.

Problem

DGX Spark GB10 (SM121) cannot use CUTLASS kernels because enable_sm120_only uses exact architecture match.

Root Cause

The existing enable_sm120_only wrapper uses:

#if defined __CUDA_ARCH__ && __CUDA_ARCH__ == 1200

This excludes SM121 (arch 1210) which has identical tensor core capabilities.

Solution

Add new enable_sm120_or_later wrapper:

#if defined __CUDA_ARCH__ && __CUDA_ARCH__ >= 1200

This includes both SM120 (RTX 5090) and SM121+ (DGX Spark) architectures.

Files Changed

• csrc/cutlass_extensions/common.hpp: Add enable_sm120_or_later template
• csrc/quantization/w8a8/cutlass/c3x/scaled_mm_blockwise_sm120_fp8_dispatch.cuh: Use enable_sm120_or_later for FP8 blockwise GEMM

Testing

Tested on DGX Spark GB10 (SM121) with nvidia/NVIDIA-Nemotron-3-Nano-30B-A3B-NVFP4

Related Issues

Fixes #28589

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[gemini-code-assist]

Code Review

This pull request adds support for SM121 (DGX Spark) by introducing an enable_sm120_or_later kernel wrapper. The change is logical and consistent with the existing codebase structure. I have one suggestion to improve the long-term robustness of the new wrapper by adding an upper bound to the architecture check, which will prevent potential issues with future, incompatible GPU architectures.

[gemini-code-assist]

While using >= 1200 correctly enables this kernel for SM120 and SM121 as intended, it makes a strong assumption about forward compatibility with all future architectures. Highly-tuned kernels like this can be sensitive to changes in future hardware generations. To make this safer and more explicit, I recommend adding an upper bound to the check to limit it to the Blackwell architecture series (presumably SM12x). This will prevent potential hard-to-debug issues on future, incompatible hardware.

#if defined __CUDA_ARCH__ && (__CUDA_ARCH__ >= 1200 && __CUDA_ARCH__ < 1300)

[mgoin]

Let's update this to enable_sm120_family since "later" sounds like >= sm120

[Code4me2]

@mgoin was there anything else to do for this one? I think this PR has all the changes you wanted

[mgoin]

Thanks @Code4me2 ! Enabled CI

[Code4me2]

@mgoin is there anything else for me to do here? the checks that failed seem unrelated to the implementatino

[mgoin]

Nope just flaky CI at the moment, thanks for the ping!

[shahizat]

hi @mgoin, @Code4me2, thanks for the fix. I built it from source on a machine with a Blackwell 6000 Pro and on a machine with a 5090. On the Blackwell 6000 Pro, it works fine, but on the machine with the 5090, it does not. Am I doing something wrong?

Error log:

ValueError: NvFp4 MoE backend 'FLASHINFER_CUTLASS' does not support the deployment configuration since kernel does not support current device.`

nvidia-smi --query-gpu=compute_cap --format=csv
compute_cap
12.0
12.0

5090 machine

uv pip show vllm
Using Python 3.12.3 environment at: .vllm
Name: vllm
Version: 0.15.2rc1.dev114+g4df841fe7.d20260208.cu130

Blackwell 6000 Pro

uv pip show vllm
Using Python 3.12.3 environment at: .vllm
Name: vllm
Version: 0.15.2rc1.dev113+ga263aa614.d20260208.cu130

My steps:

uv venv .vllm --python 3.12
source .vllm/bin/activate

uv pip install --force-reinstall torch torchvision torchaudio triton --index-url https://download.pytorch.org/whl/cu130

export TORCH_CUDA_ARCH_LIST="12.0"
export CUDA_HOME=/usr/local/cuda-13
export TRITON_PTXAS_PATH=/usr/local/cuda/bin/ptxas
export PATH="${CUDA_HOME}/bin:$PATH"

git clone https://github.com/vllm-project/vllm.git
cd vllm 
python3 use_existing_torch.py 
uv pip install -r requirements/build.txt
MAX_JOBS=$(nproc) python3 setup.py bdist_wheel

uv pip install --no-deps dist/vllm*.whl
uv pip install -r requirements/common.txt

wget https://huggingface.co/nvidia/NVIDIA-Nemotron-3-Nano-30B-A3B-NVFP4/resolve/main/nano_v3_reasoning_parser.py

VLLM_USE_FLASHINFER_MOE_FP4=1 \
VLLM_FLASHINFER_MOE_BACKEND=latency \
vllm serve nvidia/NVIDIA-Nemotron-3-Nano-30B-A3B-NVFP4 \
  --served-model-name model \
  --max-num-seqs 8 \
  --tensor-parallel-size 1 \
  --max-model-len 262144 \
  --port 8000 \
  --trust-remote-code \
  --enable-auto-tool-choice \
  --tool-call-parser qwen3_coder \
  --reasoning-parser-plugin nano_v3_reasoning_parser.py \
  --reasoning-parser nano_v3 \
  --kv-cache-dtype fp8

[Code4me2]

@shahizat let me check on my setup that I was testing with. Which model were you running when it failed?