A comprehensive collection of SystemC examples progressing from foundational modules to advanced system-level simulations. This repository is intended for students, engineers, and researchers interested in learning and applying SystemC for digital hardware design and modeling.
Basic building blocks:
- adder
- MUX (2:1)
- DEMUX (1:2)
- Comparator
- Decoder (2-to-4)
- Priority Encoder (4-to-2)
Basic sequential circuits like:
- D-flipflop
- Serial in Parallel Out (SIPO) Register
- Up-Down Counter
- Shift Register
- FSM: Sequence Detector
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Modeling various synchronization and communication mechanisms:
- Ready/Valid Handshake
- FIFO Channel (blocking and non-blocking)
- Multi-stage FIFO Stream Pipeline
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Memory-Mapped I/O System
- Register Devices with Address Decoding
- Bus Arbiter (multiple master access)
-
AXI4-Lite Bus System
- AXI4-Lite Master
- AXI4-Lite Slave Memory
- Basic Read/Write Transactions
You can go to the 0-installation/ dir for more information
- SystemC 2.3.1a
- g++ with C++98 support
- GTKWave (for waveform viewing)
- Linux OS (Ubuntu recommended)
Contributions are welcome and appreciated!
If you'd like to contribute to this project — whether it's fixing bugs, improving documentation, adding new SystemC examples, or refactoring code — please follow the steps below:
-
Fork the repository
Click the “Fork” button in the top right corner of the repo page. -
Clone your forked repository
git clone https://github.com/rezaAdinepour/systrmC-examples.git cd systrmC-examples -
Create a new branch
git checkout -b feature/your-feature-name
-
Make your changes and commit them
git add . git commit -m "Add: your description of the change"
-
Push to your fork
git push origin feature/your-feature-name
-
Create a Pull Request
- Go to the original repository (this one).
- Click “Compare & pull request”.
- Add a meaningful description and submit.