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This allows to netlist ports when power is unset. The assumption is that the user then wants a terminated (passive) load.
Bumps [pillow](https://github.com/python-pillow/Pillow) from 12.1.1 to 12.2.0. - [Release notes](https://github.com/python-pillow/Pillow/releases) - [Changelog](https://github.com/python-pillow/Pillow/blob/main/CHANGES.rst) - [Commits](python-pillow/Pillow@12.1.1...12.2.0) --- updated-dependencies: - dependency-name: pillow dependency-version: 12.2.0 dependency-type: direct:production ... Signed-off-by: dependabot[bot] <[email protected]>
…w-12.2.0 Bump pillow from 12.1.1 to 12.2.0 in /qucs/python
- Fix equations format - Auto-update Qucs-S version More details at https://github.com/andresmmera/qucs-s-spar-viewer/releases/tag/v2026.04.14
This disables the port as a source (AC and transient) and makes it a passive termination only.
fix(port): handle empty case (terminated port)
Update qucs-s-spar-viewer submodule to v2026.04.14
Previously it only ran the `.count()` after a subcircuit match, causing the number of pins always to be equal to that of the subckt definition line. Now we always increment the counter whenever we append a pin.
… dialog In the case where one has malformed input from the dialog, one could end up with a segfault due to out-of-bounds access on Ports. This guards (and reports using qWarning) multiple potential issues with inputs.
Update IT translation
Previously, it was always set to '.sch'.
When generating a netlist for a schematic without active simulation components, the simulations list is empty. Accessing `simulations.first()` caused a crash. This patch adds a safety guard and ensures the netlist is still validly terminated with `.END`.
fix(Xyce): prevent segfault when netlisting without simulations
fix(saveAs): append '.sym' for symbol files
fix(SpiceLibComp): pin parsing and dialog input validation
Fixed SPICE entry for MOSFET if parameters defined as variables and prepare for v26.1.1 release
Update SP Viewer submodule pointer
ra3xdh
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