Discussions

• 1 You must be logged in to vote

  🙏

  Genus synth of CVA6: empty module + feed-through/unloaded warnings — expected?

  hareemrashid-arcanasemi asked Feb 16, 2026 in Q&A · Unanswered

  

  

  0
• 1 You must be logged in to vote

  🙏

  Undefined symbols for architecture arm64

  jsjl3 asked Feb 5, 2026 in Q&A · Unanswered

  

  

  0
• 1 You must be logged in to vote

  🙏

  [l1 icache] cl_hit signal must be hot1

  Leeconfig asked Nov 19, 2025 in Q&A · Unanswered

  

  

  0
• 1 You must be logged in to vote

  🙏

  Branch predictor flush missing signal. Bug?

  gm-openchip asked Nov 6, 2025 in Q&A · Unanswered

  

  

  0
• 1 You must be logged in to vote

  💬

  Any interest in adding OpenROAD build support to cva6 repository

  oharboe started Jul 13, 2025 in General · Closed

  

  

  1
• 1 You must be logged in to vote

  🙏

  Bottom 128 bits of icache data_sram unused

  povik asked Jun 10, 2025 in Q&A · Answered

  

  

  

  

  3
• 1 You must be logged in to vote

  🙏

  Monitor instruction flowing into the pipeline through ILA on FPGA

  gm-openchip asked Jun 10, 2025 in Q&A · Closed · Unanswered

  

  

  0
• 1 You must be logged in to vote

  💡

  move MIMPID when bugs are fixed

  bjdooks-ct started May 29, 2025 in Ideas

  

  

  2
• 1 You must be logged in to vote

  💬

  When will the CV-X-IF interface support Memory Interface and Memory result interface?

  NoahBraasch started May 19, 2025 in General

  

  

  0
• 2 You must be logged in to vote

  💡

  H’vjh

  olti30 started Apr 8, 2025 in Ideas

  

  

  

  

  2
• 1 You must be logged in to vote

  🙏

  How to get the design files separately to use for verification and synthesis in cadence or other tools

  RakeshpatilLB asked Mar 25, 2025 in Q&A · Unanswered

  

  

  0
• 1 You must be logged in to vote

  🙏

  How to get the design files separately to use for verification and synthesis in cadence or other tools

  RakeshpatilLB asked Mar 25, 2025 in Q&A · Unanswered

  

  

  0
• 1 You must be logged in to vote

  💬

  QuestaSim flow

  omahieux-oc started Feb 27, 2025 in General · Closed

  

  

  0
• 1 You must be logged in to vote

  💬

  Add a peripheral with an interrupt source

  librlib started Jan 14, 2025 in General

  

  

  0
• 1 You must be logged in to vote

  🙏

  Read/Write of Data in cache subsystem

  Irsaliah asked Dec 12, 2024 in Q&A · Unanswered

  

  

  0
• 2 You must be logged in to vote

  🙏

  Required SRAM size for CVA6

  AAnand-Git asked Sep 13, 2024 in Q&A · Unanswered

  

  

  0
• 1 You must be logged in to vote

  💬

  Welcome to CVA6 Discussions!

  zarubaf started Dec 14, 2020 in General

  

  

  

  

  5
• 2 You must be logged in to vote

  🙏

  Steps to run bare metal code on implemented CVA6 core

  yadu-kr asked Dec 21, 2023 in Q&A · Unanswered

  

  

  0
• 7 You must be logged in to vote

  🙏

  Creating Vivado project

  kristopher391 asked Sep 12, 2023 in Q&A · Unanswered

  

  

  1
• 1 You must be logged in to vote

  🙏

  Seeking explanation of some variable in Makefile!

  AnikBalo asked Jun 8, 2023 in Q&A · Unanswered

  

  

  0
• 1 You must be logged in to vote

  🙏

  How can I generate VCD while performing cva6 rtl simulation in questasim?

  AnikBalo asked May 23, 2023 in Q&A · Unanswered

  

  

  0
• 3 You must be logged in to vote

  🙏

  Is the hypervisor extension functional in the feat/hyp-upstream branch?

  Teofil98 asked May 20, 2023 in Q&A · Unanswered

  

  

  0
• 0 You must be logged in to vote

  🙏

  Illegal instruction at start of ram during Questa simulation

  artakarakelyan asked Dec 14, 2022 in Q&A · Answered

  

  

  3
• 1 You must be logged in to vote

  🙏

  create IP core from github code

  jimaandro asked Mar 5, 2023 in Q&A · Closed · Unanswered

  

  

  0
• 1 You must be logged in to vote

  🙏

  How to use uart for printf and other console output calls in bare metal program?

  artakarakelyan asked Dec 25, 2022 in Q&A · Unanswered

  

  

  1