GitHub - liou05202798/VLSI_proeject: This frequency divider is able to divide the clock signal depending on 3-bit input signal. Also, we were required to draw block diagrams to represent the structure, use “laker” to layout, use another software to simulate the different after doing layout, and analyze delay and power consumption.

Branches Tags

Name		Name	Last commit message	Last commit date
Latest commit History 2 Commits
VLSI		VLSI
.DS_Store		.DS_Store
106061173_106011101_Final_Project.gds		106061173_106011101_Final_Project.gds
106061173_106011101_Final_Project.pdf		106061173_106011101_Final_Project.pdf
106061173_106011101_Final_tb.sp		106061173_106011101_Final_tb.sp
106061173_106011101_post_sim.sp		106061173_106011101_post_sim.sp
106061173_106011101_pre_sim.sp		106061173_106011101_pre_sim.sp

About

This frequency divider is able to divide the clock signal depending on 3-bit input signal. Also, we were required to draw block diagrams to represent the structure, use “laker” to layout, use another software to simulate the different after doing layout, and analyze delay and power consumption.

layout waveview hspice virtuoso