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ayakayorihiro
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Feb 19, 2026
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This is looking good! I left a couple of comments about things we should change before we merge.
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Sorry, since we're writing all of this - can you also add some documentation about adding primitives to firrtl option too (which is to just add the SystemVerilog implementation of the primitive to primitives-for-firrtl.sv)?
docs/running-calyx/firrtl.md
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| ### Adding Primitives for `firrtl-with-primitives` | ||
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| 1. **Create a Template:** Add a `.fir` file to `tools/firrtl/templates/`. The filename should match the primitive name (e.g., `std_add.fir`). | ||
| 2. **Define the Interface:** The template must define a `module` whose ports (names and widths) exactly match the `extmodule` emitted by the Calyx backend in `calyx/backend/src/firrtl.rs`. |
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Hm, I don't think the FIRRTL backend emits extmodules when we use it for firrtl-with-primitives (the build.ninja file in the generated fud2 directory will show you this, we can look through this next wednesday if you'd like). Maybe you mean something else?
| 1. **Create a Template:** Add a `.fir` file to `tools/firrtl/templates/`. The filename should match the primitive name (e.g., `std_add.fir`). | ||
| 2. **Define the Interface:** The template must define a `module` whose ports (names and widths) exactly match the `extmodule` emitted by the Calyx backend in `calyx/backend/src/firrtl.rs`. | ||
| 3. **Update the Replacement Map:** If your primitive uses unique parameters, update the replacement map logic in `tools/firrtl/generate-firrtl-with-primitives.py`. | ||
| 4. **Testing:** Add a `runt` test in `tests/firrtl/primitive-templates` to ensure the new implementation generates valid FIRRTL and produces correct simulation results. |
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