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[Bug] CSR writes to cycle/instret do not raise illegal-instruction

Status: Open.

#465 In SpinalHDL/VexRiscv;

· canxin121 opened on Nov 24, 2025

[Bug] VexRiscv FSGNJX.D Sign Bit Wrong

Status: Open.

#464 In SpinalHDL/VexRiscv;

· canxin121 opened on Nov 24, 2025

Compatibility with OpenSBI 1.6 or newer

Status: Open.

#462 In SpinalHDL/VexRiscv;

· mineiwik opened on Nov 22, 2025

How to add RV32IMAF instructions to a modified Murax SoC?

Status: Open.

#461 In SpinalHDL/VexRiscv;

· Usutatsu opened on Nov 13, 2025

Briey Soc + HDMI +SD_card

Status: Open.

#460 In SpinalHDL/VexRiscv;

· Nauqchix opened on Nov 13, 2025

Question about VexRiscv Debug Interface and onChipRam Behavior in Murax on Arty-A7

Status: Open.

#459 In SpinalHDL/VexRiscv;

· Usutatsu opened on Nov 5, 2025

Seeking Advice on Murax SoC RAM Access and Floating-Point Support

Status: Open.

#458 In SpinalHDL/VexRiscv;

· Usutatsu opened on Oct 22, 2025

Fails with <code>scala.NotImplementedError: an implementation is missing</code>

Status: Open.

#456 In SpinalHDL/VexRiscv;

· RossComputerGuy opened on Oct 19, 2025

How to configure the on-chip RAM size

Status: Open.

#452 In SpinalHDL/VexRiscv;

· Rithik260 opened on Jun 8, 2025

Integrating vhdl using Blackbox

Status: Open.

#451 In SpinalHDL/VexRiscv;

· karegoud opened on Jun 4, 2025

Porting FREERTOS to VexRiscv

Status: Open.

#448 In SpinalHDL/VexRiscv;

· nerdylye opened on Apr 21, 2025

Vexriscv dual-core smp architecture has a problem when debugging

Status: Open.

#446 In SpinalHDL/VexRiscv;

· MasterWJi opened on Mar 11, 2025