fix(fpga): replace Diff2AXI shifting to vec indexing for congestion

[xiaokamikami]

• Cut the wide Gateway->Host path with a register slice to reduce long routes.

• Replace 16008-bit per-beat shift with beat-indexed serialization to shrink active cones.

• Intended to ease routing congestion and improve PCIe-clock timing.

[klin02]

Maybe rebase the master and test again?

[klin02]

@copilot Give a short commit message, like previous commit message in this repo.

[Copilot]

@copilot Give a short commit message, like previous commit message in this repo.

Done — updated in c8142c4: refactor(fpga): pipeline batch bus and beat-serialize AXIS

[github-actions]

Current result (nutshell) - 2026-04-11 21:14

Instance	Module	Total LUTs	Logic LUTs	LUTRAMs	SRLs	FFs	RAMB36	RAMB18	URAM	DSP Blocks
U_CPU_TOP	SimTop_wrapper	114083 (2.9%)	104779	9304	0	92853	17	13	4	16
nutcore	NutCore	16587 (0.4%)	16427	160	0	20989	17	9	0	16
difftest_host	HostEndpoint	14009 (0.4%)	4865	9144	0	31962	0	0	0	0
endpoint	GatewayEndpoint	81112 (2.0%)	81112	0	0	37443	0	0	0	0

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Archive (latest, 20260410)

Instance	Module	Total LUTs	Logic LUTs	LUTRAMs	SRLs	FFs	RAMB36	RAMB18	URAM	DSP Blocks
U_CPU_TOP	SimTop_wrapper	125502 (3.1%)	116198	9304	0	93057	17	13	4	16
nutcore	NutCore	16587 (0.4%)	16427	160	0	20989	17	9	0	16
difftest_host	HostEndpoint	25417 (0.6%)	16273	9144	0	32155	0	0	0	0
endpoint	GatewayEndpoint	81123 (2.0%)	81123	0	0	37454	0	0	0	0