Vector whole register load(vl2re32.v) partially updates destination on exception

[zhangkanqi]

Before start

• I have read the RISC-V ISA Manual and this is not a RISC-V ISA question. 我已经阅读过 RISC-V 指令集手册，这不是一个指令集本身的问题。
• I have read the XiangShan Documents. 我已经阅读过香山文档。
• I have searched the previous issues and did not find anything relevant. 我已经搜索过之前的 issue，并没有找到相关的。
• I have reviewed the commit messages from the relevant commit history. 我已经浏览过相关的提交历史和提交信息。
• I have reproduced the incorrect behaviors using the latest commit on the master branch. 我已经使用 master 分支最新的 commit 复现了不正确的行为。

Branch

kunminghu-v3

Describe the bug

When a vector whole register load instruction (vl2re32.v) triggers a Load Access Fault exception on the first element, XiangShan incorrectly updates both the destination vector register and the vstart CSR, violating RISC-V Vector Extension's precise exception requirements.

Instruction & Context:

vl2re32.v v18, (s4)

Register values at exception:

• Base address (s4): 0x0000000000000007 (invalid address)
• vl: 7
• vstart (before): 0
• vtype: 0x00000000000000c0 (e8, m1, ta, ma)

Expected behavior

According to RISC-V Vector Extension v1.0 Specification Section 17.1 (Precise vector traps):

...., while the vstart CSR contains the element index on which the trap was taken.

Precise vector traps require that:
...
3. any operations within the trapping vector instruction affecting result elements preceding the index in the vstart CSR have committed their results;
4. no operations within the trapping vector instruction affecting elements at or following the vstart CSR have altered architectural state except if restarting and completing the affected vector instruction will nevertheless produce the correct final state.

Since the first memory access (element 0 at address 0x07) triggers an exception:

Expected behavior (NEMU):

• v18: 0x4f1f4b1690b83a06_6248950be5c263f4 (unchanged)
• vstart: 0x0000000000000000 (element 0 caused the trap)
• Exception triggered normally

Actual Behavior(XiangShan):

• v18_low: 0x6248950b00000000 (partially overwritten - low 32 bits cleared)
• vstart: 0x0000000000000001 (incorrectly incremented)

Mismatch details:

emu compiled at Apr  6 2026, 02:30:36
Using simulated 32768B flash
Core  0's Commit SHA is: fb0b7e3ea7, dirty: 1
Using simulated 8386560MB RAM
The image is testcases/vl2re32_vstrat_v18partial.img
The reference model is riscv64-nemu-interpreter-so
The first instruction of core 0 has commited. Difftest enabled. 
�[1;34m[src/memory/paddr.c:240,check_paddr] isa pmp check failed, vaddr=0x0000000080002184, paddr=0x0000000080002184, len=0x4, type=0x1, mode=0x3�[0m
�[1;34m[src/memory/paddr.c:240,check_paddr] isa pmp check failed, vaddr=0x0000000000000007, paddr=0x0000000000000007, len=0x4, type=0x1, mode=0x3�[0m

============== Commit Group Trace (Core 0) ==============
commit group [00]: pc 0080001008 cmtcnt 1
commit group [01]: pc 008000100c cmtcnt 1
commit group [02]: pc 008000103c cmtcnt 1
commit group [03]: pc 0080001000 cmtcnt 1
commit group [04]: pc 0080001004 cmtcnt 1
commit group [05]: pc 0080001008 cmtcnt 1
commit group [06]: pc 008000100c cmtcnt 1
commit group [07]: pc 0080001044 cmtcnt 1
commit group [08]: pc 0080001000 cmtcnt 1
commit group [09]: pc 0080001004 cmtcnt 1
commit group [10]: pc 0080001008 cmtcnt 1
commit group [11]: pc 008000100c cmtcnt 1
commit group [12]: pc 008000104c cmtcnt 1
commit group [13]: pc 0080001050 cmtcnt 1
commit group [14]: pc 0080001054 cmtcnt 1
commit group [15]: pc 0080001058 cmtcnt 1 <--

============== Commit Instr Trace ==============
[00] commit pc 0000000080000216 inst f40787d3 wen 1 dst 15 data ffffffffffff17a9 idx 001 fmv.h.x fa5, a5
[01] commit pc 000000008000021a inst 00002f97 wen 1 dst 31 data 000000008000221a idx 002 auipc   t6, 0x2
[02] commit pc 000000008000021e inst e56f8f93 wen 1 dst 31 data 0000000080002070 idx 003 addi    t6, t6, -426
[03] commit pc 0000000080000222 inst 5ff0006f wen 0 dst 00 data ffffffd4853e6000 idx 004 j       pc + 0xdfe
[04] commit pc 0000000080001020 inst 60000d93 wen 1 dst 27 data 0000000000000600 idx 005 li      s11, 1536
[05] commit pc 0000000080001024 inst 300da073 wen 0 dst 00 data 0000000000000600 idx 006 csrs    mstatus, s11
[06] commit pc 0000000080001028 inst cc03f2d7 wen 1 dst 05 data 0000000000000007 idx 007 vsetivli t0, 7, e8, m1, ta, ma
[07] commit pc 000000008000102c inst 0252e03b wen 0 dst 00 data 0000000000000007 idx 008 remw    zero, t0, t0
[08] commit pc 0000000080001030 inst b0802373 wen 1 dst 06 data 0000000000000000 idx 009 (S) csrr    t1, mhpmcounter8
[09] commit pc 0000000080001034 inst 053a05d7 wen 1 dst 11 data 0000000000000000 idx 00a vandn.vv v11, v19, v20, v0.t
[10] exception pc 0000000080001038 inst 606fb3af cause 0000000000000007 amoand.d t2, t1, (t6)
[11] commit pc 0000000080001000 inst 341026f3 wen 1 dst 13 data 0000000080001038 idx 00b csrr    a3, mepc
[12] commit pc 0000000080001004 inst 00468693 wen 1 dst 13 data 000000008000103c idx 00c addi    a3, a3, 4
[13] commit pc 0000000080001008 inst 34169073 wen 0 dst 00 data 000000008000103c idx 00d csrw    mepc, a3
[14] commit pc 000000008000100c inst 30200073 wen 0 dst 00 data 000000008000103c idx 00e mret
[15] commit pc 000000008000103c inst e20f9ed3 wen 1 dst 29 data 0000000000000040 idx 00f fclass.d t4, ft11
[16] exception pc 0000000080001040 inst ab86a277 cause 0000000000000002 vaeskf2.vi v4, v24, 13
[17] commit pc 0000000080001000 inst 341026f3 wen 1 dst 13 data 0000000080001040 idx 010 csrr    a3, mepc
[18] commit pc 0000000080001004 inst 00468693 wen 1 dst 13 data 0000000080001044 idx 011 addi    a3, a3, 4
[19] commit pc 0000000080001008 inst 34169073 wen 0 dst 00 data 0000000080001044 idx 012 csrw    mepc, a3
[20] commit pc 000000008000100c inst 30200073 wen 0 dst 00 data 0000000080001044 idx 013 mret
[21] commit pc 0000000080001044 inst 0a5eb733 wen 1 dst 14 data 0000000000000000 idx 014 clmulh  a4, t4, t0
[22] exception pc 0000000080001048 inst 114fa407 cause 0000000000000005 flw     fs0, 276(t6)
[23] commit pc 0000000080001000 inst 341026f3 wen 1 dst 13 data 0000000080001048 idx 015 csrr    a3, mepc
[24] commit pc 0000000080001004 inst 00468693 wen 1 dst 13 data 000000008000104c idx 016 addi    a3, a3, 4
[25] commit pc 0000000080001008 inst 34169073 wen 0 dst 00 data 000000008000104c idx 017 csrw    mepc, a3
[26] commit pc 000000008000100c inst 30200073 wen 0 dst 00 data 000000008000104c idx 018 mret
[27] commit pc 000000008000104c inst 28e29a33 wen 1 dst 20 data 0000000000000007 idx 019 bset    s4, t0, a4
[28] commit pc 0000000080001050 inst 0000100f wen 0 dst 00 data 0000000000000007 idx 01a fence.i
[29] commit pc 0000000080001054 inst 69eb1b13 wen 1 dst 22 data 0000000040000000 idx 01b binvi   s6, s6, 30
[30] commit pc 0000000080001058 inst 2963c433 wen 1 dst 08 data e2e2e2e200e2e2e2 idx 01c xperm8 (args unknown)
[31] exception pc 000000008000105c inst 228a6907 cause 0000000000000005 vl2re32.v v18, (s4) <--

==============  REF Regs  ==============
---------------- Intger Registers ----------------
  $0: 0x0000000000000000   ra: 0x17a03d5c0bff6a72   sp: 0xb726910256bc1eac   gp: 0x0086bcf246e7d8e0 
  tp: 0xde64edbb5a037a26   t0: 0x0000000000000007   t1: 0x0000000000000000   t2: 0xe5678e918aa0b7e2 
  s0: 0xe2e2e2e200e2e2e2   s1: 0xe6644a917f44d6e7   a0: 0x09f44e579123515a   a1: 0x9978b2b80b63165c 
  a2: 0xcd4ef7c2a9019c30   a3: 0x000000008000104c   a4: 0x0000000000000000   a5: 0xa90a7cc151ce17a9 
  a6: 0x0000000000000000   a7: 0x0000000000000000   s2: 0x0000000000000000   s3: 0x0000000000000000 
  s4: 0x0000000000000007   s5: 0x0000000000000000   s6: 0x0000000040000000   s7: 0x0000000000000000 
  s8: 0x0000000000000000   s9: 0x0000000000000000  s10: 0x0000000000000000  s11: 0x0000000000000600 
  t3: 0x0000000000000000   t4: 0x0000000000000040   t5: 0x0000000000000000   t6: 0x0000000080002070 
---------------- Float Registers ----------------
 ft0: 0xffffffff00000000  ft1: 0xffffffffffff6a72  ft2: 0xb726910256bc1eac  ft3: 0xffffffff46e7d8e0 
 ft4: 0xffffffffffff7a26  ft5: 0xffffffffffff5901  ft6: 0xffffffffffff7d86  ft7: 0xffffffffffffb7e2 
 fs0: 0xffffffff027f745d  fs1: 0xffffffff7f44d6e7  fa0: 0xffffffff9123515a  fa1: 0xffffffffffff165c 
 fa2: 0xffffffffa9019c30  fa3: 0xffffffffffffcf57  fa4: 0xffffffffffffc4bc  fa5: 0xffffffffffff17a9 
 fa6: 0x156703ca5ed7557e  fa7: 0x9b1458dc52deab45  fs2: 0x941d1edbef0f0a22  fs3: 0xee88cd0c7f71a378 
 fs4: 0x2a43e3b50899d0b9  fs5: 0x8f01cdd1865f0c82  fs6: 0x680056216b93da00  fs7: 0x2ac6d24536f9bb26 
 fs8: 0xce62b34329f01f0c  fs9: 0xbd3f95d2c6ca0c6a fs10: 0xf70be3466132c48d fs11: 0x4246502b34411727 
 ft8: 0x1141c23849a3d278  ft9: 0x98762e7440c155c1 ft10: 0xf1ffd2e1f166e0f5 ft11: 0x0ecdbd982576a4a0 
 fcsr: 0x0000000000000020 fflags: 0x0000000000000000 frm: 0x0000000000000001
---------------- Privileged CSRs ----------------
pc: 0x0000000080001000  privilege mode: M (mode: 3  v: 0  debug: 0)
   mstatus: 0x8000040a006e7fa0   sstatus: 0x80000002000c6720  vsstatus: 0x0000000200000000
   hstatus: 0x0000000200000000  mnstatus: 0x0000000000000008
    mcause: 0x0000000000000005      mepc: 0x000000008000105c     mtval: 0x0000000000000007
    scause: 0x0000000000000000      sepc: 0x0000000000000000     stval: 0x0000000000000000
   vscause: 0x0000000000000000     vsepc: 0x0000000000000000    vstval: 0x0000000000000000
   mncause: 0x0000000000000000     mnepc: 0x0000000000000000 mnscratch: 0x0000000000000000
    mtval2: 0x0000000000000000     htval: 0x0000000000000000
    mtinst: 0x0000000000000000    htinst: 0x0000000000000000
  mscratch: 0xd12fdb5644d90ee9  sscratch: 0xfe20b4e29c7aff24 vsscratch: 0xe2d872842db635bf
     mtvec: 0x0000000080001000     stvec: 0x0000000080001010    vstvec: 0x0000000000000000
       mip: 0x0000000000000000       mie: 0x0000000000000000
   mideleg: 0x0000000000001444   medeleg: 0x0000000000000000
   hideleg: 0x0000000000000000   hedeleg: 0x0000000000000000
      satp: 0x0000000000000000     hgatp: 0x0000000000000000     vsatp: 0x0000000000000000
 mcounteren: 0x0000000000000000 scounteren: 0x0000000000000000 hcounteren: 0x0000000000000000
  miselect: 0x0000000000000000  siselect: 0x0000000000000000 vsiselect: 0x0000000000000000
     mireg: 0x0000000000000000     sireg: 0x0000000000000000    vsireg: 0x0000000000000000
     mtopi: 0x0000000000000000     stopi: 0x0000000000000000    vstopi: 0x0000000000000000
     mvien: 0x0000000000000000     hvien: 0x0000000000000000      mvip: 0x0000000000000000
    mtopei: 0x0000000000000000    stopei: 0x0000000000000000   vstopei: 0x0000000000000000
    hvictl: 0x0000000000000000  hviprio1: 0x0000000000000000  hviprio2: 0x0000000000000000
---------------- PMP CSRs ----------------
pmp: 32 entries active, details:
 0: cfg:0x00 addr:0x0000000000000000| 1: cfg:0x00 addr:0x0000000000000000
 2: cfg:0x00 addr:0x0000000000000000| 3: cfg:0x00 addr:0x0000000000000000
 4: cfg:0x00 addr:0x0000000000000000| 5: cfg:0x00 addr:0x0000000000000000
 6: cfg:0x00 addr:0x0000000000000000| 7: cfg:0x00 addr:0x0000000000000000
 8: cfg:0x00 addr:0x0000000000000000| 9: cfg:0x00 addr:0x0000000000000000
10: cfg:0x00 addr:0x0000000000000000|11: cfg:0x00 addr:0x0000000000000000
12: cfg:0x00 addr:0x0000000000000000|13: cfg:0x00 addr:0x0000000000000000
14: cfg:0x00 addr:0x0000000000000000|15: cfg:0x00 addr:0x0000000000000000
16: cfg:0x00 addr:0x0000000000000000|17: cfg:0x00 addr:0x0000000000000000
18: cfg:0x00 addr:0x0000000000000000|19: cfg:0x00 addr:0x0000000000000000
20: cfg:0x00 addr:0x0000000000000000|21: cfg:0x00 addr:0x0000000000000000
22: cfg:0x00 addr:0x0000000000000000|23: cfg:0x00 addr:0x0000000000000000
24: cfg:0x00 addr:0x0000000000000000|25: cfg:0x00 addr:0x0000000000000000
26: cfg:0x00 addr:0x0000000000000000|27: cfg:0x00 addr:0x0000000000000000
28: cfg:0x00 addr:0x0000000000000000|29: cfg:0x00 addr:0x0000000000000000
30: cfg:0x00 addr:0x0000000000000000|31: cfg:0x00 addr:0x0000000000000000
32: cfg:0x00 addr:0x0000000000000000|33: cfg:0x00 addr:0x0000000000000000
34: cfg:0x00 addr:0x0000000000000000|35: cfg:0x00 addr:0x0000000000000000
36: cfg:0x00 addr:0x0000000000000000|37: cfg:0x00 addr:0x0000000000000000
38: cfg:0x00 addr:0x0000000000000000|39: cfg:0x00 addr:0x0000000000000000
40: cfg:0x00 addr:0x0000000000000000|41: cfg:0x00 addr:0x0000000000000000
42: cfg:0x00 addr:0x0000000000000000|43: cfg:0x00 addr:0x0000000000000000
44: cfg:0x00 addr:0x0000000000000000|45: cfg:0x00 addr:0x0000000000000000
46: cfg:0x00 addr:0x0000000000000000|47: cfg:0x00 addr:0x0000000000000000
48: cfg:0x00 addr:0x0000000000000000|49: cfg:0x00 addr:0x0000000000000000
50: cfg:0x00 addr:0x0000000000000000|51: cfg:0x00 addr:0x0000000000000000
52: cfg:0x00 addr:0x0000000000000000|53: cfg:0x00 addr:0x0000000000000000
54: cfg:0x00 addr:0x0000000000000000|55: cfg:0x00 addr:0x0000000000000000
56: cfg:0x00 addr:0x0000000000000000|57: cfg:0x00 addr:0x0000000000000000
58: cfg:0x00 addr:0x0000000000000000|59: cfg:0x00 addr:0x0000000000000000
60: cfg:0x00 addr:0x0000000000000000|61: cfg:0x00 addr:0x0000000000000000
62: cfg:0x00 addr:0x0000000000000000|63: cfg:0x00 addr:0x0000000000000000
---------------- PMA CSRs ----------------
pma: 32 entries active, details:
 0: cfg:0x00 addr:0x0000000000000000| 1: cfg:0x00 addr:0x0000000000000000
 2: cfg:0x00 addr:0x0000000000000000| 3: cfg:0x00 addr:0x0000000000000000
 4: cfg:0x00 addr:0x0000000000000000| 5: cfg:0x00 addr:0x0000000000000000
 6: cfg:0x00 addr:0x0000000000000000| 7: cfg:0x00 addr:0x0000000000000000
 8: cfg:0x00 addr:0x0000000000000000| 9: cfg:0x00 addr:0x0000000000000000
10: cfg:0x00 addr:0x0000000000000000|11: cfg:0x00 addr:0x0000000000000000
12: cfg:0x00 addr:0x0000000000000000|13: cfg:0x00 addr:0x0000000000000000
14: cfg:0x00 addr:0x0000000000000000|15: cfg:0x00 addr:0x0000000000000000
16: cfg:0x00 addr:0x0000000000000000|17: cfg:0x00 addr:0x0000000000000000
18: cfg:0x00 addr:0x0000000000000000|19: cfg:0x0b addr:0x0000000004000000
20: cfg:0x0f addr:0x0000000008000000|21: cfg:0x0b addr:0x000000000c004000
22: cfg:0x0b addr:0x000000000c014000|23: cfg:0x0b addr:0x000000000e008000
24: cfg:0x0f addr:0x000000000e008400|25: cfg:0x0b addr:0x000000000e008800
26: cfg:0x0b addr:0x000000000e400000|27: cfg:0x0b addr:0x000000000e400800
28: cfg:0x08 addr:0x000000000e800000|29: cfg:0x0b addr:0x0000000020000000
30: cfg:0x6f addr:0x0000020000000000|31: cfg:0x18 addr:0x00001fffffffffff
---------------- Vector Registers ----------------
v0 : 0x40d684bd4869864e_933a8f6cca53ee2d  v1 : 0xa352582891e553b4_f6fa77f1c81f7dd4  
v2 : 0x605e706555f7a860_96fc703eb6c38d94  v3 : 0x3a2faccf88f1d289_20847e7606be887d  
v4 : 0x8f61549f7206a80d_a5534dbe2d494608  v5 : 0x274ba61216281af6_fd4f3a0bad5bc9d3  
v6 : 0x312916de98eab4e7_42ad8c11b880c2f7  v7 : 0xc33b6587c13ebc36_5f84bc904a24475e  
v8 : 0xe1dd57a300e46e57_51bd6a0d663db9de  v9 : 0xb0661952a23232cd_fc9c5e55945635f4  
v10: 0xd3def3721041a4f8_97c185ca2cba73e5  v11: 0xffffffffffffffff_ffff62ff301cff02  
v12: 0x5a1495e9017471b9_1b47fc7547301d8b  v13: 0x9b7a55295dc21901_db8c80ef5e697abe  
v14: 0x2bcd620c2b3bdec4_8d8667f98a995d6e  v15: 0xb994b41cb36c7734_d041aeffd28d0b75  
v16: 0xa5513f9b9b92d117_329b8e1fbf8a5361  v17: 0xc3cb4beb00c5ebd8_fbd1f3ca1d133ea1  
v18: 0x4f1f4b1690b83a06_6248950be5c263f4  v19: 0x78660a8b6ec8d4ed_de2b679038dc775b  
v20: 0x216f16361d091af7_159e1d210ee2d1d9  v21: 0x795d168d78741945_2098972ef68581dc  
v22: 0x3dbc301acc699808_dee16938a018c9ca  v23: 0xd7b384230a0aadd1_90da85f5a01cefaa  
v24: 0xd24a450333fd81e2_e11627112d99c78f  v25: 0xeee87911b73b0e2e_b11a169ca9907f51  
v26: 0xe81cee5eaad4f124_aa7e0045230e9720  v27: 0xbf49870d32070b43_56cd92b64bb90407  
v28: 0x37e3cfe621e7d91a_349024f6ab76b6b3  v29: 0xb8a3155d89f12c27_21505b3fbe60817b  
v30: 0xdeeaf8877dc147fe_ad09f2a9bd6b72a6  v31: 0xcbd012690d3a600d_f81ec038420a9867  
  vtype: 0x00000000000000c0 vstart: 0x0000000000000000  vxsat: 0x0000000000000001
   vxrm: 0x0000000000000000     vl: 0x0000000000000007   vcsr: 0x0000000000000001
---------------- Triggers ----------------
 tselect: 0x0000000000000000
 0: tdata1: 0xf000000000000000 tdata2: 0x0000000000000000
 1: tdata1: 0xf000000000000000 tdata2: 0x0000000000000000
 2: tdata1: 0xf000000000000000 tdata2: 0x0000000000000000
 3: tdata1: 0xf000000000000000 tdata2: 0x0000000000000000
 4: tdata1: 0x0000000000000000 tdata2: 0x0000000000000000
privilegeMode: 3
v18_low different at pc = 0x0080001058, right = 0x6248950be5c263f4, wrong = 0x6248950b00000000
 vstart different at pc = 0x0080001058, right = 0x0000000000000000, wrong = 0x0000000000000001
Core 0: �[31mABORT at pc = 0x800001ec
�[0m�[35mCore-0 instrCnt = 188, cycleCnt = 1,727, IPC = 0.108859
�[0m�[34mSeed=0 Guest cycle spent: 1,731 (this will be different from cycleCnt if emu loads a snapshot)
�[0m�[34mHost time spent: 2,383ms
�[0m

Environment

XiangShan:
version: commit fb0b7e3
build command:

time make DISABLE_PERF=1 emu CONFIG=MinimalConfig EMU_THREADS=2 -j$(nproc)

NEMU:
version: commit d046c0e9d6560f9c2f068e3973c9a7f904d6881c
config: riscv64-xs-ref_defconfig

For other environmental information, please refer to the compressed file.

To Reproduce

./build/emu -i vl2re32_vstrat_v18partial.img --diff riscv64-nemu-interpreter-so

where riscv64-nemu-interpreter-so is NEMU(commit: d046c0e9d6560f9c2f068e3973c9a7f904d6881c) built with riscv64-xs-ref_defconfig

vl2re32_vstrat_v18partial_mismatch.zip

Additional context

No response

[sinceforYy]

Thanks for your issue.

The kunminghu-v3 branch is currently under development and refactoring, and it is normal to have bugs at the moment. These bugs will be fixed later.

If you want to test vectors, you can test them on stable kunminghu-v2 branch.