NMSIS: support the terapines libdsp and libnn function libraries. by kaishaoshao · Pull Request #65 · Nuclei-Software/nuclei-sdk

kaishaoshao · 2025-12-24T08:02:00Z

No description provided.

Signed-off-by: dongyongtao <dongyongtao@nucleisys.com>

RT-Thread/ThreadX/FreeRTOS/UCOSII support are updated see https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-cc.adoc The stack grows downwards (towards lower addresses) and the stack pointer shall be aligned to a 128-bit boundary upon procedure entry. The ILP32E calling convention is designed to be usable with the RV32E ISA. This calling convention is the same as the integer calling convention, except for the following differences. The stack pointer need only be aligned to a 32-bit boundary.

Make task frame 16 bytes aligned by changing saved regs from 30 to 32 https://github.com/riscv-mcu/riscv-gcc/blob/553a166de2dd7451652a0973908e1f2459118506/gcc/config/riscv/riscv.h#L201-L211 Signed-off-by: Huaqi Fang <578567190@qq.com>

…t 16 bytes aligned This will make sure sp is 16 bytes aligned when call c function in task switch process see 1c24496

… enabled Signed-off-by: Huaqi Fang <578567190@qq.com>

Signed-off-by: dongyongtao <dongyongtao@nucleisys.com>

…eRTOS SMP The previous implementation of `vPortRecursiveLock` was unsafe on systems with weak memory ordering (like RISC-V), leading to potential race conditions. This commit corrects the implementation by introducing necessary memory barriers and optimizes the spin-wait loop. **Correctness Fixes:** * **Acquire Barrier**: An acquire memory barrier (`__RWMB()`) is added immediately after a successful atomic swap (`__AMOSWAP_W`). This is critical to prevent the compiler or CPU from reordering memory operations from within the critical section to before the lock is actually acquired. Without this, the lock provides no protection. * **Release Barrier**: A release memory barrier (`__RWMB()`) is added before the lock variable is cleared. This ensures that all memory writes within the critical section are globally visible *before* the lock is released. This prevents other cores from acquiring the lock and seeing stale data. **Performance and Logic Improvements:** * **Test-and-Test-and-Set (TTS)**: The lock acquisition logic has been restructured into a more efficient TTS pattern. The code now spins on a cheap, non-atomic read (`while (*pxSpinLock == 0)`) and only attempts the expensive atomic swap when the lock appears to be free. This significantly reduces bus contention and improves system performance when multiple cores are contending for a lock. * **NOP in Spin Loop**: A `__NOP()` has been added to the spin-wait loop. This can help reduce power consumption and pipeline pressure on some CPU architectures during tight spins. * **Improved Readability**: Added comments to clarify the logic for recursive locking, lock acquisition, and the purpose of the memory barriers. Signed-off-by: Huaqi Fang <578567190@qq.com>

The `ucOwnedByCore` and `ucRecursionCountByLock` arrays are used to manage recursive spinlocks and are accessed by multiple cores. Without the `volatile` keyword, the compiler might optimize away memory accesses and cache the array values in registers. This could lead to a core reading a stale value, causing incorrect lock behavior, race conditions, or deadlocks in a multi-core environment. Marking these arrays as `volatile` ensures that every access reads from or writes to main memory, guaranteeing the correct and up-to-date state is observed by all cores. Signed-off-by: Huaqi Fang <578567190@qq.com>

n300e is rv32emac, n300e is added in build system, npk and doc Signed-off-by: Huaqi Fang <578567190@qq.com>

…anges Signed-off-by: Huaqi Fang <578567190@qq.com>

This application demonstrates how to switch from machine mode to user mode on Nuclei RISC-V processors. It showcases the usage of PMP (Physical Memory Protection) configuration, ECLIC (Enhanced Core-Local Interrupt Controller) interrupt handling, and SysTimer functionality.

- Add safety recommendation for changing MTH: - Disable all interrupts before modifying MTH - Perform fence operation after changing MTH - Re-enable interrupts after the changes - Similar recommendation added for setting STH

Set MTH maybe not effective right now, it is neccessary to disable/enable interrupt for criticial mth set routine - Add code to disable interrupts before setting BASEPRI in vPortRaiseBASEPRI, ulPortRaiseBASEPRI, and vPortSetBASEPRI functions - This change ensures proper synchronization and prevents potential race conditions when modifying the BASEPRI register

…rt functions It may racely met a eclic mth setted, but interrupt still goes in, and then mth modified by other tasks switched in, and then return to previous vPortEnterCritical will face a assert Here configASSERT((__ECLIC_GetMth() & portMTH_MASK) == uxMaxSysCallMTH); - Add MSTATUS_MIE save and restore in vPortRaiseBASEPRI, ulPortRaiseBASEPRI, and vPortSetBASEPRI functions - Ensure interrupts are disabled before setting MTH to prevent potential race conditions

The sPMP and sMPU entries currently supported are limited up to 16 - Add conditional compilation to limit SPMP and SMPU entry numbers to 16 - Preserve original logic for cases where CFG_PMP_ENTRY_NUM <= 16 - Improve compatibility with systems having more than 16 PMP entries

…king - Add support for using MSTATUS.MIE instead of ECLIC.MTH for interrupt masking when configMAX_SYSCALL_INTERRUPT_PRIORITY >= 255 - Update port.c and portmacro.h to handle both interrupt masking methods - Modify FreeRTOSConfig.h files to set configMAX_SYSCALL_INTERRUPT_PRIORITY to 255 - Add comments to explain the behavior of configMAX_SYSCALL_INTERRUPT_PRIORITY

- Remove unnecessary kernel debug and assertion code - Eliminate redundant critical section management functions - Simplify interrupt enable/disable macros - Remove unused variables and functions related to max syscall priority - Optimize task switching and tick handling - The original portable code is modified based on FreeRTOS, now this port just use mie to do interrupt masking Signed-off-by: Huaqi Fang <578567190@qq.com>