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applet.iterface.uart_pinout: UART pinout applet #1012

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applet.iterface.uart_pinout: UART pinout applet #1012

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53538b4
gateware.uart: Create `ExternalUART`
drosseau-ivision Aug 22, 2025
83d1926
applet.interface: Create the uart-pinout applet
drosseau-ivision Aug 25, 2025
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5 changes: 3 additions & 2 deletions software/glasgow/applet/interface/uart/__init__.py
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Original file line number Diff line number Diff line change
Expand Up @@ -10,7 +10,7 @@
from glasgow.support.arepl import AsyncInteractiveConsole
from glasgow.support.logging import dump_hex
from glasgow.support.endpoint import ServerEndpoint
from glasgow.gateware.uart import UART
from glasgow.gateware.uart import ExternalUART
from glasgow.abstract import AbstractAssembly, GlasgowPin
from glasgow.applet import GlasgowAppletV2

Expand Down Expand Up @@ -117,7 +117,8 @@ def elaborate(self, platform):
# TODO: `uart.bit_cyc` is only used to set the width of the register; the actual initial
# value is zero (same as `self.bit_cyc`); this is a footgun and should be fixed by rewriting
# the UART to use lib.wiring
m.submodules.uart = uart = UART(self.ports,
m.submodules.uart = uart = ExternalUART(
self.ports,
bit_cyc=(1 << len(self.manual_cyc)) - 1,
parity=self.parity)
m.submodules.auto_baud = auto_baud = UARTAutoBaud()
Expand Down
8 changes: 5 additions & 3 deletions software/glasgow/applet/interface/uart_analyzer/__init__.py
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Original file line number Diff line number Diff line change
Expand Up @@ -11,7 +11,7 @@
from amaranth.lib.wiring import In, Out

from glasgow.gateware.ports import PortGroup
from glasgow.gateware.uart import UART
from glasgow.gateware.uart import ExternalUART
from glasgow.gateware.stream import Queue
from glasgow.abstract import AbstractAssembly, GlasgowPin, ClockDivisor
from glasgow.applet import GlasgowAppletV2, GlasgowAppletError
Expand Down Expand Up @@ -51,8 +51,10 @@ def elaborate(self, platform):

channels = []
for index, pin in enumerate(self._port):
m.submodules[f"ch{index}"] = uart = UART(PortGroup(rx=pin),
bit_cyc=(1 << len(self.periods[index])) - 1, parity=self._parity)
m.submodules[f"ch{index}"] = uart = ExternalUART(
PortGroup(rx=pin),
bit_cyc=(1 << len(self.periods[index])) - 1,
parity=self._parity)
m.d.comb += uart.bit_cyc.eq(self.periods[index] + 1)
channels.append(uart)

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