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Add BitflagRegister
Register with simple 1 bit flags
1 parent 3d304b9 commit fec7a1e

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riscvmodel/types.py

Lines changed: 39 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -313,6 +313,45 @@ def __iadd__(self, other):
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self.update(self.reg.value + other)
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return self.reg
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class BitflagRegister():
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def __init__(self, flags: list, *, prefix=""):
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assert isinstance(flags, list) and len(flags) > 0
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super().__setattr__("flags", flags)
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self.prefix = prefix
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for flag in flags:
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super().__setattr__(flag, 0)
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super().__setattr__(flag+"_update", None)
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def __setattr__(self, name, value):
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if name in self.flags:
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super().__setattr__(name+"_update", value)
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else:
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super().__setattr__(name, value)
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def set(self, value):
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for flag in value:
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assert flag in self.flags
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setattr(self, flag, value[flag])
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def get(self, flag):
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assert flag in self.flags
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return getattr(self, flag)
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def changes(self):
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changes = []
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for flag in self.flags:
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upd = getattr(self, flag+"_update")
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if upd is not None:
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changes.append(TraceRegister(self.prefix+flag, upd))
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return changes
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def commit(self):
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for flag in self.flags:
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upd = getattr(self, flag+"_update")
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if upd is not None:
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super().__setattr__(flag, upd)
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super().__setattr__(flag+"_update", None)
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class Trace(object):
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pass
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