Adding execution implementation for atomic instructions:

 * Model now tracks atomic acquire and release
 * Single stage single HART implementations of LR, SC, and AMO*
   instructions now exist in insn.py
 * Basic test sequence for LR & SC defined in tests_atomic.py
 * Fixed issues with pytest tests

Author: Peter Birch

riscvmodel/insn.py

@@ -487,85 +487,186 @@ def execute(self, model: Model):
 class InstructionLR(InstructionAMOType):
     """ Load reserved """
     def execute(self, model: Model):
-        # TODO: implement
-        pass
+        # Perform a normal load
+        data = model.state.memory.lw(model.state.intreg[self.rs1].unsigned())
+        model.state.intreg[self.rd] = data
+        # Perform correct lock or release actions
+        if self.rl: model.state.atomic_release(model.state.intreg[self.rs1])
+        elif self.aq: model.state.atomic_acquire(model.state.intreg[self.rs1])
 
 
 @isa("sc", RV32A, opcode=0b0101111, funct5=0b00011, funct3=0b010)
 class InstructionSC(InstructionAMOType):
     """ Store conditional """
     def execute(self, model: Model):
-        # TODO: implement
-        pass
+        # Check if this address is reserved
+        if model.state.atomic_reserved(model.state.intreg[self.rs1]):
+            model.state.memory.sw(
+                model.state.intreg[self.rs1].unsigned(),
+                model.state.intreg[self.rs2]
+            )
+            model.state.intreg[self.rd] = 0
+        else:
+            model.state.intreg[self.rd] = 1
+        # Perform correct lock or release actions
+        if self.rl: model.state.atomic_release(model.state.intreg[self.rs1])
+        elif self.aq: model.state.atomic_acquire(model.state.intreg[self.rs1])
 
 
 @isa("amoadd", RV32A, opcode=0b0101111, funct5=0b00000, funct3=0b010)
 class InstructionAMOADD(InstructionAMOType):
-    """ Atomic swap operation """
+    """ Atomic add operation """
     def execute(self, model: Model):
-        # TODO: implement
-        pass
+        # This models a single HART with 1 stage pipeline, so will always succeed
+        model.state.intreg[self.rd] = model.state.memory.lw(
+            model.state.intreg[self.rs1].unsigned()
+        )
+        model.state.memory.sw(
+            model.state.intreg[self.rs1].unsigned(),
+            (model.state.intreg[self.rs2] + model.state.intreg[self.rd])
+        )
+        # Perform correct lock or release actions
+        if self.rl: model.state.atomic_release(model.state.intreg[self.rs1])
+        elif self.aq: model.state.atomic_acquire(model.state.intreg[self.rs1])
 
 
 @isa("amoxor", RV32A, opcode=0b0101111, funct5=0b00100, funct3=0b010)
 class InstructionAMOXOR(InstructionAMOType):
-    """ Atomic swap operation """
+    """ Atomic XOR operation """
     def execute(self, model: Model):
-        # TODO: implement
-        pass
+        # This models a single HART with 1 stage pipeline, so will always succeed
+        model.state.intreg[self.rd] = model.state.memory.lw(
+            model.state.intreg[self.rs1].unsigned()
+        )
+        model.state.memory.sw(
+            model.state.intreg[self.rs1].unsigned(),
+            (model.state.intreg[self.rs2] ^ model.state.intreg[self.rd])
+        )
+        # Perform correct lock or release actions
+        if self.rl: model.state.atomic_release(model.state.intreg[self.rs1])
+        elif self.aq: model.state.atomic_acquire(model.state.intreg[self.rs1])
 
 
 @isa("amoor",   RV32A, opcode=0b0101111, funct5=0b01000, funct3=0b010)
 class InstructionAMOOR(InstructionAMOType):
-    """ Atomic swap operation """
+    """ Atomic OR operation """
     def execute(self, model: Model):
-        # TODO: implement
-        pass
+        # This models a single HART with 1 stage pipeline, so will always succeed
+        model.state.intreg[self.rd] = model.state.memory.lw(
+            model.state.intreg[self.rs1].unsigned()
+        )
+        model.state.memory.sw(
+            model.state.intreg[self.rs1].unsigned(),
+            (model.state.intreg[self.rs2] | model.state.intreg[self.rd])
+        )
+        # Perform correct lock or release actions
+        if self.rl: model.state.atomic_release(model.state.intreg[self.rs1])
+        elif self.aq: model.state.atomic_acquire(model.state.intreg[self.rs1])
 
 
 @isa("amoand", RV32A, opcode=0b0101111, funct5=0b01100, funct3=0b010)
 class InstructionAMOAND(InstructionAMOType):
-    """ Atomic swap operation """
+    """ Atomic AND operation """
     def execute(self, model: Model):
-        # TODO: implement
-        pass
+        # This models a single HART with 1 stage pipeline, so will always succeed
+        model.state.intreg[self.rd] = model.state.memory.lw(
+            model.state.intreg[self.rs1].unsigned()
+        )
+        model.state.memory.sw(
+            model.state.intreg[self.rs1].unsigned(),
+            (model.state.intreg[self.rs2] & model.state.intreg[self.rd])
+        )
+        # Perform correct lock or release actions
+        if self.rl: model.state.atomic_release(model.state.intreg[self.rs1])
+        elif self.aq: model.state.atomic_acquire(model.state.intreg[self.rs1])
 
 
 @isa("amomin", RV32A, opcode=0b0101111, funct5=0b10000, funct3=0b010)
 class InstructionAMOMIN(InstructionAMOType):
-    """ Atomic swap operation """
+    """ Atomic minimum operation """
     def execute(self, model: Model):
-        # TODO: implement
-        pass
+        # This models a single HART with 1 stage pipeline, so will always succeed
+        model.state.intreg[self.rd] = model.state.memory.lw(
+            model.state.intreg[self.rs1].unsigned()
+        )
+        model.state.memory.sw(
+            model.state.intreg[self.rs1].unsigned(),
+            min(model.state.intreg[self.rs2], model.state.intreg[self.rd])
+        )
+        # Perform correct lock or release actions
+        if self.rl: model.state.atomic_release(model.state.intreg[self.rs1])
+        elif self.aq: model.state.atomic_acquire(model.state.intreg[self.rs1])
 
 
 @isa("amomax", RV32A, opcode=0b0101111, funct5=0b10100, funct3=0b010)
 class InstructionAMOMAX(InstructionAMOType):
-    """ Atomic swap operation """
+    """ Atomic maximum operation """
     def execute(self, model: Model):
-        # TODO: implement
-        pass
+        # This models a single HART with 1 stage pipeline, so will always succeed
+        model.state.intreg[self.rd] = model.state.memory.lw(
+            model.state.intreg[self.rs1].unsigned()
+        )
+        model.state.memory.sw(
+            model.state.intreg[self.rs1].unsigned(),
+            max(model.state.intreg[self.rs2], model.state.intreg[self.rd])
+        )
+        # Perform correct lock or release actions
+        if self.rl: model.state.atomic_release(model.state.intreg[self.rs1])
+        elif self.aq: model.state.atomic_acquire(model.state.intreg[self.rs1])
 
 
 @isa("amominu", RV32A, opcode=0b0101111, funct5=0b11000, funct3=0b010)
 class InstructionAMOMINU(InstructionAMOType):
-    """ Atomic swap operation """
-    def execute(self, model: Model):
-        # TODO: implement
-        pass
+    """ Atomic unsigned minimum operation """
+    def execute(self, model: Model):
+        # This models a single HART with 1 stage pipeline, so will always succeed
+        model.state.intreg[self.rd] = model.state.memory.lw(
+            model.state.intreg[self.rs1].unsigned()
+        )
+        model.state.memory.sw(
+            model.state.intreg[self.rs1].unsigned(),
+            min(
+                model.state.intreg[self.rs2].unsigned(),
+                model.state.intreg[self.rd].unsigned()
+            )
+        )
+        # Perform correct lock or release actions
+        if self.rl: model.state.atomic_release(model.state.intreg[self.rs1])
+        elif self.aq: model.state.atomic_acquire(model.state.intreg[self.rs1])
 
 
 @isa("amomaxu", RV32A, opcode=0b0101111, funct5=0b11100, funct3=0b010)
 class InstructionAMOMAXU(InstructionAMOType):
-    """ Atomic swap operation """
-    def execute(self, model: Model):
-        # TODO: implement
-        pass
+    """ Atomic unsigned maximum operation """
+    def execute(self, model: Model):
+        # This models a single HART with 1 stage pipeline, so will always succeed
+        model.state.intreg[self.rd] = model.state.memory.lw(
+            model.state.intreg[self.rs1].unsigned()
+        )
+        model.state.memory.sw(
+            model.state.intreg[self.rs1].unsigned(),
+            max(
+                model.state.intreg[self.rs2].unsigned(),
+                model.state.intreg[self.rd].unsigned()
+            )
+        )
+        # Perform correct lock or release actions
+        if self.rl: model.state.atomic_release(model.state.intreg[self.rs1])
+        elif self.aq: model.state.atomic_acquire(model.state.intreg[self.rs1])
 
 
 @isa("amoswap", RV32A, opcode=0b0101111, funct5=0b00001, funct3=0b010)
 class InstructionAMOSWAP(InstructionAMOType):
     """ Atomic swap operation """
     def execute(self, model: Model):
-        # TODO: implement
-        pass
+        # This models a single HART with 1 stage pipeline, so will always succeed
+        model.state.intreg[self.rd] = model.state.memory.lw(
+            model.state.intreg[self.rs1].unsigned()
+        )
+        model.state.memory.sw(
+            model.state.intreg[self.rs1].unsigned(),
+            model.state.intreg[self.rs2]
+        )
+        # Perform correct lock or release actions
+        if self.rl: model.state.atomic_release(model.state.intreg[self.rs1])
+        elif self.aq: model.state.atomic_acquire(model.state.intreg[self.rs1])

riscvmodel/isa.py

@@ -851,10 +851,3 @@ def get_mnemomics():
     """
     return [i.mnemonic for i in get_insns()]
 
-class TerminateException(Exception):
-    """
-    Exception that signal the termination of the program
-    """
-    def __init__(self, returncode):
-        super().__init__()
-        self.returncode = returncode

riscvmodel/model.py

@@ -5,6 +5,14 @@
 from .types import Register, RegisterFile, TracePC, TraceIntegerRegister, TraceMemory
 from .program import Program
 
+class TerminateException(Exception):
+    """
+    Exception that signal the termination of the program
+    """
+    def __init__(self, returncode):
+        super().__init__()
+        self.returncode = returncode
+
 # todo: raise exception on memory misalignment
 class State(object):
     single_regs = []
@@ -17,6 +25,8 @@ def __init__(self, variant: Variant):
         self.pc_update = Register(32)
         self.memory = Memory()
         self.initialized = True
+        # Used for tracking atomic accesses
+        self.reservations = []
 
     def randomize(self):
         self.intreg.randomize()
@@ -44,10 +54,19 @@ def __setattr__(self, key, value):
         else:
             super().__setattr__(key, value)
 
-
     def __str__(self):
         return "{}".format(self.intreg)
 
+    def atomic_acquire(self, address):
+        if not address in self.reservations:
+            self.reservations.append(address)
+
+    def atomic_release(self, address):
+        if address in self.reservations:
+            self.reservations.remove(address)
+
+    def atomic_reserved(self, address):
+        return address in self.reservations
 
 class Memory(object):
     def __init__(self, *, base: int = 0, size: int = 2^32):

riscvmodel/program/tests.py

@@ -1,4 +1,5 @@
 from riscvmodel.isa import *
+from riscvmodel.insn import *
 from riscvmodel.regnames import *
 from riscvmodel.program import Program
 

riscvmodel/program/tests_atomic.py

@@ -0,0 +1,25 @@
+from riscvmodel.isa import *
+from riscvmodel.insn import *
+from riscvmodel.regnames import *
+from riscvmodel.program import Program
+
+
+class LRSCTest(Program):
+    """Basic test of LR & SC instructions"""
+    def __init__(self):
+        super().__init__([
+            # Perform load-reserved and acquire lock
+            InstructionLR(rs1=x0, rd=x1, aq=1, rl=0),
+            # Perform store-conditional and release lock (should succeed)
+            InstructionSC(rs1=x0, rs2=x0, rd=x2, aq=0, rl=1),
+            # Perform second store-conditional to same address (should fail)
+            InstructionSC(rs1=x0, rs2=x0, rd=x3, aq=0, rl=1),
+        ])
+
+    def expects(self) -> dict:
+        return {
+            x0: 0,
+            x2: 0, # Due to successful SC (2nd instruction)
+            x3: 1, # Due to failed SC (3rd instruction)
+        }
+

tests/test_model.py

@@ -1,6 +1,7 @@
 from riscvmodel.program.tests import *
+from riscvmodel.program.tests_atomic import *
 from riscvmodel.model import Model
-from riscvmodel.variant import RV32I
+from riscvmodel.variant import RV32I, RV32A
 
 import pytest
 
@@ -21,3 +22,11 @@ def test_model_addi():
     m = Model(RV32I)
     m.execute(pgm)
     check_model(m, pgm.expects())
+
+
+def test_model_lr_sc():
+    """Test if load-reserved and store-conditional sequence works"""
+    pgm = LRSCTest()
+    m   = Model(RV32A)
+    m.execute(pgm)
+    check_model(m, pgm.expects())