all: clang-format: apply LambdaBodyIndentation=OuterScope

Author: dzarukin

.clang-format

@@ -83,6 +83,7 @@ IndentPPDirectives: None
 IndentWidth:     4
 IndentWrappedFunctionNames: false
 KeepEmptyLinesAtTheStartOfBlocks: true
+LambdaBodyIndentation : OuterScope
 MacroBlockBegin: ''
 MacroBlockEnd:   ''
 MaxEmptyLinesToKeep: 1

examples/rnn_training_f32.cpp

@@ -172,8 +172,8 @@ void simple_net(engine::kind engine_kind) {
 
     // Create auxiliary f32 memory descriptor
     // based on user- supplied dimensions and layout.
-    auto formatted_md = [=](const memory::dims &dimensions,
-                                memory::format_tag layout) {
+    auto formatted_md
+            = [=](const memory::dims &dimensions, memory::format_tag layout) {
         return memory::desc {{dimensions}, memory::data_type::f32, layout};
     };
     // Create auxiliary generic f32 memory descriptor

examples/ukernels/cpu_brgemm.cpp

@@ -121,9 +121,9 @@ void brgemm_example() {
     // Initialize binary_add.
     std::generate(
             binary_add_user_data.begin(), binary_add_user_data.end(), []() {
-                static int i = 3;
-                return i++ % 6;
-            });
+        static int i = 3;
+        return i++ % 6;
+    });
     // Initialize B scales.
     std::generate(B_scales_user_data.begin(), B_scales_user_data.end(), []() {
         static int i = 4;

src/common/cache_utils.hpp

@@ -289,20 +289,19 @@ struct lru_cache_t final : public cache_t<K, O, C, key_merge> {
             auto it = std::min_element(cache_mapper().begin(),
                     cache_mapper().end(),
                     [&](const v_t &left, const v_t &right) {
-                        // By default, load() and operator T use sequentially
-                        // consistent memory ordering, which enforces writing
-                        // the timestamps into registers in the same exact order
-                        // they are read from the CPU cache line. Since eviction
-                        // is performed under a write lock, this order is not
-                        // important, therefore we can safely use the weakest
-                        // memory ordering (relaxed). This brings about a few
-                        // microseconds performance improvement for default
-                        // cache capacity.
-                        return left.second.timestamp_.load(
-                                       std::memory_order_relaxed)
-                                < right.second.timestamp_.load(
-                                        std::memory_order_relaxed);
-                    });
+                // By default, load() and operator T use sequentially
+                // consistent memory ordering, which enforces writing
+                // the timestamps into registers in the same exact order
+                // they are read from the CPU cache line. Since eviction
+                // is performed under a write lock, this order is not
+                // important, therefore we can safely use the weakest
+                // memory ordering (relaxed). This brings about a few
+                // microseconds performance improvement for default
+                // cache capacity.
+                return left.second.timestamp_.load(std::memory_order_relaxed)
+                        < right.second.timestamp_.load(
+                                std::memory_order_relaxed);
+            });
             auto res = cache_mapper().erase(it->first);
             MAYBE_UNUSED(res);
             assert(res);

src/common/dnnl_thread.hpp

@@ -306,23 +306,20 @@ static inline void parallel(int nthr, const std::function<void(int, int)> &f) {
 #endif
     }
 #elif DNNL_CPU_THREADING_RUNTIME == DNNL_RUNTIME_TBB
-    tbb::parallel_for(
-            0, nthr,
-            [&](int ithr) {
+    tbb::parallel_for(0, nthr, [&](int ithr) {
 #if defined(DNNL_ENABLE_ITT_TASKS)
-                bool mark_task = itt::primitive_task_get_current_kind()
-                        == primitive_kind::undefined;
-                if (mark_task && itt_enable)
-                    itt::primitive_task_start(task_primitive_kind,
-                            task_primitive_info, task_primitive_log_kind);
+        bool mark_task = itt::primitive_task_get_current_kind()
+                == primitive_kind::undefined;
+        if (mark_task && itt_enable)
+            itt::primitive_task_start(task_primitive_kind, task_primitive_info,
+                    task_primitive_log_kind);
 #endif
-                f(ithr, nthr);
+        f(ithr, nthr);
 #if defined(DNNL_ENABLE_ITT_TASKS)
-                if (mark_task && itt_enable)
-                    itt::primitive_task_end(task_primitive_log_kind);
+        if (mark_task && itt_enable)
+            itt::primitive_task_end(task_primitive_log_kind);
 #endif
-            },
-            tbb::static_partitioner());
+    }, tbb::static_partitioner());
 #elif DNNL_CPU_THREADING_RUNTIME == DNNL_RUNTIME_THREADPOOL
     using namespace dnnl::impl::threadpool_utils;
     dnnl::threadpool_interop::threadpool_iface *tp = get_active_threadpool();

src/common/memory_desc_wrapper.hpp

@@ -240,12 +240,12 @@ struct memory_desc_wrapper : public c_compatible {
 
         auto calculate_size
                 = [ndims, &pdims](int cmask, size_t buff_data_size) {
-                      assert(utils::one_of(cmask, 1, 2, 3, 5, 13, 27));
-                      dim_t prod = 1;
-                      for (int d = 0; d < ndims; ++d)
-                          if (cmask & (1 << d)) { prod *= pdims[d]; }
-                      return (size_t)prod * buff_data_size;
-                  };
+            assert(utils::one_of(cmask, 1, 2, 3, 5, 13, 27));
+            dim_t prod = 1;
+            for (int d = 0; d < ndims; ++d)
+                if (cmask & (1 << d)) { prod *= pdims[d]; }
+            return (size_t)prod * buff_data_size;
+        };
 
         if (flag == compensation_conv_s8s8) {
             return calculate_size(extra().compensation_mask,

src/common/memory_zero_pad.cpp

@@ -93,40 +93,40 @@ void typed_zero_pad_blk(const memory_desc_wrapper &m_d, void *data_handle) {
     if (c_tail_s) {
         parallel_nd(A, B, D, E, F,
                 [=](dim_t a, dim_t b, dim_t d, dim_t e, dim_t f) {
-                    auto x = &data[m_d.blk_off(a, b, C - 1, d, e, f)];
-                    if (blk_kind == c)
-                        zeroize_tail(x, c_tail_s);
-                    else if (blk_kind == bc)
-                        zeroize_tail_inner(x, c_tail_s);
-                    else if (blk_kind == cb)
-                        zeroize_tail_outer(x, c_tail_s);
-                });
+            auto x = &data[m_d.blk_off(a, b, C - 1, d, e, f)];
+            if (blk_kind == c)
+                zeroize_tail(x, c_tail_s);
+            else if (blk_kind == bc)
+                zeroize_tail_inner(x, c_tail_s);
+            else if (blk_kind == cb)
+                zeroize_tail_outer(x, c_tail_s);
+        });
     }
 
     if (b_tail_s) {
         parallel_nd(A, C, D, E, F,
                 [=](dim_t a, dim_t c, dim_t d, dim_t e, dim_t f) {
-                    auto x = &data[m_d.blk_off(a, B - 1, c, d, e, f)];
-                    if (blk_kind == b)
-                        zeroize_tail(x, b_tail_s);
-                    else if (blk_kind == ab || blk_kind == cb)
-                        zeroize_tail_inner(x, b_tail_s);
-                    else if (blk_kind == ba || blk_kind == bc)
-                        zeroize_tail_outer(x, b_tail_s);
-                });
+            auto x = &data[m_d.blk_off(a, B - 1, c, d, e, f)];
+            if (blk_kind == b)
+                zeroize_tail(x, b_tail_s);
+            else if (blk_kind == ab || blk_kind == cb)
+                zeroize_tail_inner(x, b_tail_s);
+            else if (blk_kind == ba || blk_kind == bc)
+                zeroize_tail_outer(x, b_tail_s);
+        });
     }
 
     if (a_tail_s) {
         parallel_nd(B, C, D, E, F,
                 [=](dim_t b, dim_t c, dim_t d, dim_t e, dim_t f) {
-                    auto x = &data[m_d.blk_off(A - 1, b, c, d, e, f)];
-                    if (blk_kind == a)
-                        zeroize_tail(x, a_tail_s);
-                    else if (blk_kind == ba)
-                        zeroize_tail_inner(x, a_tail_s);
-                    else if (blk_kind == ab)
-                        zeroize_tail_outer(x, a_tail_s);
-                });
+            auto x = &data[m_d.blk_off(A - 1, b, c, d, e, f)];
+            if (blk_kind == a)
+                zeroize_tail(x, a_tail_s);
+            else if (blk_kind == ba)
+                zeroize_tail_inner(x, a_tail_s);
+            else if (blk_kind == ab)
+                zeroize_tail_outer(x, a_tail_s);
+        });
     }
 }
 

src/common/type_helpers.hpp

@@ -1212,10 +1212,10 @@ inline status_t memory_desc_init_by_blocking_desc(
 
     utils::simultaneous_sort(
             mblk.strides, ou_blocks, perm, ndims, [](stride_t a, stride_t b) {
-                if (utils::one_of(DNNL_RUNTIME_DIM_VAL, a, b))
-                    return DNNL_RUNTIME_DIM_VAL;
-                return b - a;
-            });
+        if (utils::one_of(DNNL_RUNTIME_DIM_VAL, a, b))
+            return DNNL_RUNTIME_DIM_VAL;
+        return b - a;
+    });
 
     dim_t stride = block_size;
     for (int _d = ndims - 1; _d >= 0; --_d) {

src/common/verbose.cpp

@@ -446,20 +446,20 @@ std::string md2fmt_tag_str(const memory_desc_t *md) {
     //   output tag: acdb
     std::sort(sort_keys.begin(), sort_keys.end(),
             [](const sort_key_t &left, const sort_key_t &right) {
-                if (left.stride_order < right.stride_order) return false;
-                if (left.stride_order == right.stride_order) {
-                    // WLOG, we can assume a dimension of size 1 has the same
-                    // stride as the next outermost dimension. Sort the one with
-                    // the non-unit outer block as the outer dimension. Multiple
-                    // dimensions of size 1 with the same stride is ambiguous.
-                    if (left.outer_block < right.outer_block) return false;
-                    if (left.outer_block == right.outer_block)
-                        // Sort 1x1x... outer blocks to (arbitrarily) list them
-                        // in alphabetical order.
-                        return left.idx < right.idx;
-                }
-                return true;
-            });
+        if (left.stride_order < right.stride_order) return false;
+        if (left.stride_order == right.stride_order) {
+            // WLOG, we can assume a dimension of size 1 has the same
+            // stride as the next outermost dimension. Sort the one with
+            // the non-unit outer block as the outer dimension. Multiple
+            // dimensions of size 1 with the same stride is ambiguous.
+            if (left.outer_block < right.outer_block) return false;
+            if (left.outer_block == right.outer_block)
+                // Sort 1x1x... outer blocks to (arbitrarily) list them
+                // in alphabetical order.
+                return left.idx < right.idx;
+        }
+        return true;
+    });
 
     char dim_chars[DNNL_MAX_NDIMS + 1];
     for (int i = 0; i < mdw.ndims(); ++i)

src/cpu/aarch64/cpu_barrier.hpp

@@ -33,14 +33,13 @@ namespace simple_barrier {
 
 #define CTX_ALIGNMENT 4096
 
-STRUCT_ALIGN(
-        CTX_ALIGNMENT, struct ctx_t {
-            enum { CACHE_LINE_SIZE = 256 };
-            volatile size_t ctr;
-            char pad1[CACHE_LINE_SIZE - 1 * sizeof(size_t)];
-            volatile size_t sense;
-            char pad2[CACHE_LINE_SIZE - 1 * sizeof(size_t)];
-        });
+STRUCT_ALIGN(CTX_ALIGNMENT, struct ctx_t {
+    enum { CACHE_LINE_SIZE = 256 };
+    volatile size_t ctr;
+    char pad1[CACHE_LINE_SIZE - 1 * sizeof(size_t)];
+    volatile size_t sense;
+    char pad2[CACHE_LINE_SIZE - 1 * sizeof(size_t)];
+});
 
 /* TODO: remove ctx_64_t once batch normalization switches to barrier-less
  * implementation.
@@ -49,14 +48,13 @@ STRUCT_ALIGN(
  * stable with page alignment compared to cache line size alignment.
  * Batch normalization (that creates C / simd_w barriers) degrades with page
  * alignment due to significant overhead of ctx_init in case of mb=1. */
-STRUCT_ALIGN(
-        256, struct ctx_64_t {
-            enum { CACHE_LINE_SIZE = 256 };
-            volatile size_t ctr;
-            char pad1[CACHE_LINE_SIZE - 1 * sizeof(size_t)];
-            volatile size_t sense;
-            char pad2[CACHE_LINE_SIZE - 1 * sizeof(size_t)];
-        });
+STRUCT_ALIGN(256, struct ctx_64_t {
+    enum { CACHE_LINE_SIZE = 256 };
+    volatile size_t ctr;
+    char pad1[CACHE_LINE_SIZE - 1 * sizeof(size_t)];
+    volatile size_t sense;
+    char pad2[CACHE_LINE_SIZE - 1 * sizeof(size_t)];
+});
 
 template <typename ctx_t>
 inline void ctx_init(ctx_t *ctx) {