My comments

[PythonLinks]

It is hard to get good feedback, so here are my comments.

A description of why this design is better than other designs would be helpful.

The image is great, but it took a while to understand it. Are those separate RAM blocks? In that case, maybe the strength of this design is high bandwidth to the memory blocks. A better introduction would have helped me understand the image the first time I looked at it.

Lots of great details. It would be nice to have a simple higher level view of the instruction set. What were you thinking when you designed this?

With all of the different memory access options, you may want to justify it using the data presented here and in the appendix.

https://users.ece.cmu.edu/~koopman/stack_computers/sec6_3.html

It is not clear which board/fpga this is running on.

It is not clear how your memory is structured. One block ram, multiple ones???

After 3 reads, I am still not sure where the wright address comes from.

It would most helpful to see the FPGA resources required by this design.

Two memory accesses per clock cycle is interesting.

Do any real Forth applications really need a 15 or 16 bit program address space. I thought that 14 bits would be plenty. Maybe I am wrong.

What frequency does this run at? Which path limits the frequency?

What happens during interrupts?

How much does this board cost?

When you define the bits such as

. These three bits define the RAM access operation.

Please specify what the options are. This cpu does a great job of it.
https://github.com/CPUNexus/Tridora-CPU-mirror/blob/main/doc/tridoracpu.md

I now see that you did this quite well with the ucode table. I am still not sure what a ucode is.

I hope that the feedback helps.

[ulixxe]

Hi, thank you for your questions about uf16. I know that the documentation is very poor, and I am committed to improve it in the future.
I try to answer to your questions:
In my implementation, I use a single 8kbyte RAM block and a single 8kbyte ROM block. Both are accessed through the same single bus (von newman architecture).
The FPGA board I used is the TinyFPGA-BX. Here there are 16 EBR blocks for the 8kbyte RAM and 16 EBR blocks for the 8kbyte ROM. You can find the FPGA resources used in the iCEcube2 log file.
These resources are used to implement the full SoC:

• uf16
• USB interface
• USB to UART interface
• Vectored interrupt controller
• Timer
• gpio

There is a single bus to access both RAM and ROM, so there is only a single access per clock cycle.
Cycle by cycle the address is generated to access the ROM for an instruction fetch, or to access the RAM for a read/write, or for a push/pop on data/return stack.
The maximum address space is 64kbyte. In the TinyFPGA-BX there are only a total of 16kbyte EBR available, so I divided them in two, 8kbyte for the ROM with the ansi 94 FORTH (almost complete, only the LEAVE word is missing) and 8kbyte for the RAM. The RAM is used for additional word definitions and for the stacks. The uf16 allows preemptive multitasking, so multiple stacks can be put in RAM, a data/return stack couple for each task.
When an interrupt is requested on irq_i input then the uf16 program counter jumps immediately to the address provided by the irqaddr_i input.
I hope that it is clearer now. Please let me know.

[PythonLinks]

Thank you.
There is now a channel for discussing Forth Hardware on the Forth Discord server. (Soft core forth machines).
https://discord.gg/fbBf46ay