Merge branch 'main' of https://github.com/ucb-bar/radiance

Author: Ruohan Yan

.github/workflows/ci.yml

@@ -152,7 +152,15 @@ jobs:
           source env.sh
           source /ecad/tools/vlsi.bashrc
           cd generators/radiance
-          python3 test/run_isa_tests.py -j "$(nproc)"
+          python3 test/run_isa_tests.py -j "$(nproc)" \
+            --json-out test/isa-test-logs/soc/results.json
+      - name: Render ISA test report
+        if: always()
+        run: |
+          cd "${CHIPYARD_DIR}/generators/radiance"
+          python3 test/render_isa_test_report.py \
+            test/isa-test-logs/soc/results.json \
+            --github-step-summary
 
   run-core-isa-tests:
     name: Run Core-standalone ISA tests
@@ -165,7 +173,15 @@ jobs:
           source env.sh
           source /ecad/tools/vlsi.bashrc
           cd generators/radiance
-          python3 test/run_isa_tests.py -j "$(nproc)" -c core
+          python3 test/run_isa_tests.py -j "$(nproc)" -c core \
+            --json-out test/isa-test-logs/core/results.json
+      - name: Render ISA test report
+        if: always()
+        run: |
+          cd "${CHIPYARD_DIR}/generators/radiance"
+          python3 test/render_isa_test_report.py \
+            test/isa-test-logs/core/results.json \
+            --github-step-summary
 
   run-cosim-isa-tests:
     name: Run Cyclotron-as-a-Tile Co-sim ISA tests
@@ -178,25 +194,41 @@ jobs:
           source env.sh
           source /ecad/tools/vlsi.bashrc
           cd generators/radiance
-          python3 test/run_isa_tests.py -j "$(nproc)" -c cosim
-
-  run-backend-cosim-isa-tests:
-    name: Run Backend Co-sim ISA tests
-    runs-on: as4
-    needs: build
-    steps:
-      - name: Run ISA tests on backend co-sim config
+          python3 test/run_isa_tests.py -j "$(nproc)" -c cosim \
+            --json-out test/isa-test-logs/cosim/results.json
+      - name: Render ISA test report
+        if: always()
         run: |
-          cd "${CHIPYARD_DIR}"
-          source env.sh
-          source /ecad/tools/vlsi.bashrc
-          cd generators/radiance
-          python3 test/run_isa_tests.py -j "$(nproc)" -c backend
+          cd "${CHIPYARD_DIR}/generators/radiance"
+          python3 test/render_isa_test_report.py \
+            test/isa-test-logs/cosim/results.json \
+            --github-step-summary
+
+  # run-backend-cosim-isa-tests:
+  #   name: Run Backend Co-sim ISA tests
+  #   runs-on: as4
+  #   needs: build
+  #   steps:
+  #     - name: Run ISA tests on backend co-sim config
+  #       run: |
+  #         cd "${CHIPYARD_DIR}"
+  #         source env.sh
+  #         source /ecad/tools/vlsi.bashrc
+  #         cd generators/radiance
+  #         python3 test/run_isa_tests.py -j "$(nproc)" -c backend \
+  #           --json-out test/isa-test-logs/backend/results.json
+  #     - name: Render ISA test report
+  #       if: always()
+  #       run: |
+  #         cd "${CHIPYARD_DIR}/generators/radiance"
+  #         python3 test/render_isa_test_report.py \
+  #           test/isa-test-logs/backend/results.json \
+  #           --github-step-summary
 
   clean:
     name: Clean
     runs-on: as4
-    needs: [build, run-unit-tests, run-soc-isa-tests, run-core-isa-tests, run-cosim-isa-tests, run-backend-cosim-isa-tests]
+    needs: [build, run-unit-tests, run-soc-isa-tests, run-core-isa-tests, run-cosim-isa-tests]
     if: always()
     steps:
       - name: Cleanup workspace, chipyard and conda

chipyard/RadianceConfigs.scala

@@ -63,15 +63,23 @@ object TapeoutSmemConfig extends RadianceSharedMemKey(
 )
 
 object L0iCacheConfig extends DCacheParams(
-  nSets = 128,
+  nSets = 512,
   nWays = 1,
   rowBits = 32 * 8,
   blockBytes = 32,
   nMSHRs = 2,
 )
 
+object L0iCacheHugeConfig extends DCacheParams(
+  nSets = 8192,
+  nWays = 1,
+  rowBits = 32 * 8,
+  blockBytes = 32,
+  nMSHRs = 4,
+)
+
 object L0dCacheConfig extends DCacheParams(
-  nSets = 512,
+  nSets = 64,
   nWays = 1,
   rowBits = 64 * 8,
   blockBytes = 64,
@@ -202,6 +210,16 @@ class RadianceSingleClusterConfig extends Config(
   new RadianceBaseConfig
 )
 
+class RadianceSingleClusterLargeICacheConfig extends Config(
+  new WithRadianceMxGemmini(location = InCluster(0), dim = 16, accSizeInKB = 32, tileSize = (8, 8, 8)) ++
+  new WithMuonCores(2, location = InCluster(0), noILP = false, l0i = Some(L0iCacheHugeConfig), l0d = Some(L0dCacheConfig), trace = true) ++
+  new WithRadianceCluster(0, smemConfig = TapeoutSmemConfig, l1Config = L1CacheConfig) ++
+  new WithExtGPUMem() ++
+  new WithRadianceRocket ++
+  new WithGPUResetAggregator(defaultReset = false) ++
+  new RadianceBaseConfig
+)
+
 class RadianceSingleClusterDiffTestConfig extends Config(
   new WithRadianceMxGemmini(location = InCluster(0), dim = 16, accSizeInKB = 32, tileSize = (8, 8, 8)) ++
   new WithMuonCores(2, location = InCluster(0), noILP = false, l0i = Some(L0iCacheConfig), l0d = Some(L0dCacheConfig), trace = true, difftest = true) ++
@@ -234,6 +252,19 @@ class RadianceLeanTapeoutSimConfig extends Config(
   new RadianceBaseConfig
 )
 
+class RadianceTapeoutSimTraceConfig extends Config(
+  new WithRadianceMxGemmini(location = InCluster(1), dim = 16, accSizeInKB = 32, tileSize = (8, 8, 8)) ++
+  new WithMuonCores(2, location = InCluster(1), noILP = false, l0i = Some(L0iCacheConfig), l0d = Some(L0dCacheConfig), trace = true) ++
+  new WithRadianceCluster(1, smemConfig = TapeoutSmemConfig, l1Config = L1CacheConfig) ++
+  new WithRadianceMxGemmini(location = InCluster(0), dim = 16, accSizeInKB = 32, tileSize = (8, 8, 8)) ++
+  new WithMuonCores(2, location = InCluster(0), noILP = false, l0i = Some(L0iCacheConfig), l0d = Some(L0dCacheConfig), trace = true) ++
+  new WithRadianceCluster(0, smemConfig = TapeoutSmemConfig, l1Config = L1CacheConfig) ++
+  new WithExtGPUMem() ++
+  new WithRadianceRocket ++
+  new WithGPUResetAggregator(defaultReset = false) ++
+  new RadianceBaseConfig
+)
+
 class RadianceTapeoutSimConfig extends Config(
   new WithRadianceMxGemmini(location = InCluster(1), dim = 16, accSizeInKB = 32, tileSize = (8, 8, 8)) ++
   new WithMuonCores(2, location = InCluster(1), noILP = false, l0i = Some(L0iCacheConfig), l0d = Some(L0dCacheConfig)) ++

cyclotron

@@ -259,6 +259,17 @@ The values of `rs1` and `rs2` are taken from the "leader" lane.
 Note: `vx_wspawn` eventually be superceded by command processor's scheduling
 capabilities.
 
+#### `vx_bar`
+
+```
+vx_bar rs1, rs2
+```
+
+Waits for `rs2` warps in a single cluster to reach barrier with id given by `rs1`. 
+The values of `rs1` and `rs2` are taken from "leader" lane. TODO: how many barriers? 16?
+
+Note: `vx_bar` will eventually be superceded by neutrino / command processor barrier mechanism
+
 ## New Registers
 
 At 128 registers, we have 96 additional registers to allocate.

docs/isa.md

@@ -225,22 +225,7 @@ class GemminiTile private (
   }
 
   // width is max output width & num output lanes
-  val requantizerSmemClient = gemminiParams.requantizer.map { q =>
-    TLClientNode(Seq(TLMasterPortParameters.v1(
-      clients = Seq(TLMasterParameters.v2(
-        name = "requantizer_out",
-        sourceId = IdRange(0, 1 << q.outputIdBits),
-        emits = TLMasterToSlaveTransferSizes(
-          putFull = TransferSizes(q.numOutputLanes * q.minOutputBits / 8,
-            q.numOutputLanes * q.maxOutputBits / 8),
-          putPartial = TransferSizes(q.numOutputLanes * q.minOutputBits / 8,
-            q.numOutputLanes * q.maxOutputBits / 8)
-        )
-      ))
-    )))
-  }
-
-  // TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLMasterParameters.v1("")))))
+  val requantizerSmemClient = None
 
   override lazy val module = new GemminiTileModuleImp(this)
 }
@@ -311,7 +296,7 @@ class GemminiTileModuleImp(outer: GemminiTile) extends BaseTileModuleImp(outer)
   // requantizer
   outer.gemminiParams.requantizer.foreach { q =>
     val in = Wire(Decoupled(new RequantizerInBundle(q.numGPUInputLanes, q.inputBits)))
-    val out = Wire(Decoupled(new RequantizerOutBundle(q.numOutputLanes, q.maxOutputBits)))
+    // val out = Wire(Decoupled(new RequantizerOutBundle(q.numOutputLanes, q.maxOutputBits)))
 
     { // input
       val (node, edge) = outer.requantizerMuonManager.get.in.head
@@ -331,40 +316,7 @@ class GemminiTileModuleImp(outer: GemminiTile) extends BaseTileModuleImp(outer)
       assert(!node.a.valid || ((node.a.bits.address & q.baseAddr.U) === q.baseAddr.U))
     }
 
-    { // output
-      val (node, edge) = outer.requantizerSmemClient.get.out.head
-
-      // data
-      val isFP4 = out.bits.dataType === RequantizerDataType.FP4
-      val fullWidth = q.numOutputLanes
-      val halfWidth = q.numOutputLanes / 2
-      node.a.bits := edge.Put(
-        fromSource = 0.U, // gets overridden
-        toAddress = out.bits.address,
-        lgSize = Mux(isFP4,
-          log2Ceil(halfWidth).U, // half byte per lane
-          log2Ceil(q.numOutputLanes).U // fp6, fp8: 1 byte per lane
-        ),
-        data = Mux(isFP4,
-          Mux(
-            out.bits.address(log2Ceil(halfWidth)), // not aligned to full line
-            (out.bits.data(halfWidth - 1, 0) << halfWidth).asTypeOf(UInt(fullWidth.W)),
-            out.bits.data
-          ),
-          out.bits.data
-        )
-      )._2
-
-      // source
-      val (sourceReady, _) = SourceGenerator(node)
-      out.ready := node.a.ready && sourceReady
-      node.a.valid := out.valid && sourceReady
-      assert(out.fire === node.a.fire)
-      node.d.ready := true.B
-    }
-
     outer.gemmini.module.mx_io.get.requant_in_gpu <> in
-    outer.gemmini.module.mx_io.get.requant_out <> out
   }
 
   // lut
@@ -420,14 +372,15 @@ class GemminiTileModuleImp(outer: GemminiTile) extends BaseTileModuleImp(outer)
 
   val gemminiBaseMMIO = Seq(
     0x00 -> Seq(RegField.w(32, gemminiCommandReg(_, _))),
+    0x08 -> Seq(RegField.r(32, gemminiIO.ready)),
     0x10 -> Seq(
       RegField.w(32, gemminiRs1RegLSB),
       RegField.w(32, gemminiRs1RegMSB)),
     0x18 -> Seq(
       RegField.w(32, gemminiRs2RegLSB),
       RegField.w(32, gemminiRs2RegMSB)),
     0x20 -> Seq(RegField.r(32, gemminiBusyReg(_))),
-    0x28 -> Seq(RegField.r(32, gemminiRunningLoopsReg(_)))
+    0x28 -> Seq(RegField.r(32, gemminiRunningLoopsReg(_))),
   )
 
   val gemminiCiscMMIO = Option.when(!outer.gemminiParams.hasAccSlave) {

src/main/scala/radiance/cluster/GemminiTile.scala

@@ -131,6 +131,7 @@ class RadianceCluster (
     cache = thisClusterParams.l1Config,
     cacheTagBits = muonTiles.head.muonParams.core.l1ReqTagBits,
     overrideDChannelSize = Some(log2Ceil(thisClusterParams.l1Config.blockBytes)),
+    makeLandingPads = true
   ))(
     p.alterMap(Map(
       TileVisibilityNodeKey -> visibilityNode,

src/main/scala/radiance/cluster/RadianceCluster.scala

@@ -2,7 +2,7 @@ package radiance.cluster
 
 import chisel3._
 import chisel3.util._
-import freechips.rocketchip.diplomacy.{AddressSet, BufferParams}
+import freechips.rocketchip.diplomacy.BufferParams
 import freechips.rocketchip.tilelink._
 import gemmini._
 import org.chipsalliance.cde.config.Parameters
@@ -162,13 +162,8 @@ class RadianceSharedMemComponents(
     .map(connectOne(_, () => RWSplitterNode(f"muon_aligned_splitter")))
   val muonAligned = Seq.fill(2)(muonSplitterNodes.map(connectXbarName(_, Some("muon_aligned_fanout"))))
 
-  val quantOutputWidth = gemminiTiles.flatMap(_.gemminiParams.requantizer
-    .map(q => q.numOutputLanes * q.maxOutputBits / 8))
-  val quantOutputNodesSingleBank = distAndDuplicate(
-    gemminiTiles.flatMap(_.requantizerSmemClient).map(x =>
-      (connectOne(x, () => AddressOrNode(clusterParams.baseAddr)), quantOutputWidth.head)
-    ), "quant_w")
-  val quantOutputNodes = Seq.fill(smemBanks)(quantOutputNodesSingleBank)
+  val quantOutputNodes = Seq.fill(smemBanks)(Seq.fill(smemSubbanks)(Seq[TLNexusNode]()))
+  // val quantOutputNodes = Seq.fill(smemBanks)(quantOutputNodesSingleBank)
 
   // connect requantizer managers directly here TODO: move outside, make smemNodes xbars
   gemminiTiles.flatMap(_.requantizerMuonManager).foreach { qm =>

src/main/scala/radiance/cluster/RadianceSharedMemComponents.scala

@@ -69,21 +69,36 @@ class FlitMergeNode(from: Int, to: Int, alwaysMerge: Boolean = true)
         val finalOut = WireInit(mergedReq)
         finalOut.data := filledData
         finalOut.mask := filledMask
+        finalOut.source := in.a.bits.source // last beat response
 
         out.a.valid := isLastReq
         out.a.bits := finalOut
-        in.a.ready := Mux(isLastReq, out.a.ready, true.B)
+        // we acknowledge all A subrequests except for the last one immediately
+        in.a.ready := Mux(isLastReq, out.a.ready, in.d.ready && !out.d.valid)
       }.otherwise {
         out.a <> in.a
       }
 
       // restore size on D channel if merged on A
-      val wasMerged = VecInit.fill(1 << out.a.bits.params.sourceBits)(false.B)
+      val wasMerged = RegInit(VecInit.fill(1 << out.a.bits.params.sourceBits)(false.B))
       when (in.a.fire) {
         wasMerged(in.a.bits.source) := shouldMerge
       }
-      in.d <> out.d
-      in.d.bits.size := Mux(wasMerged(out.d.bits.source), log2Ceil(from).U, out.d.bits.size)
+
+      // if D channel has a response, we prioritize passthru; otherwise, we try to
+      // acknowledge all but the last mergeable subrequest from A
+      in.d.valid := out.d.valid || (shouldMerge && in.a.valid && !isLastReq)
+      in.d.bits := Mux(out.d.valid, out.d.bits, ie.AccessAck(in.a.bits))
+      in.d.bits.size := Mux(
+        out.d.valid,
+        Mux(
+          wasMerged(out.d.bits.source),
+          log2Ceil(from).U,
+          out.d.bits.size
+        ),
+        log2Ceil(from).U
+      )
+      out.d.ready := in.d.ready
     }
   }
 }