mlp3layers & hls4ml synth failed

[bgvmad]

Error on synth

ERROR: [Synth 8-690] width mismatch in assignment; target has 128 bits, source has 96 bits [/home/1-HowToSetup/esp/socs/xilinx-vc707-xc7vx485t/socketgen/allacc.vhd:25]
ERROR: [Synth 8-690] width mismatch in assignment; target has 128 bits, source has 96 bits [/home/1-HowToSetup/esp/socs/xilinx-vc707-xc7vx485t/socketgen/allacc.vhd:28]
ERROR: [Synth 8-285] failed synthesizing module 'mlp3layers_hls4ml_rtl' [/home/1-HowToSetup/esp/socs/xilinx-vc707-xc7vx485t/socketgen/accelerators.vhd:45]
ERROR: [Synth 8-285] failed synthesizing module 'noc_mlp3layers_hls4ml' [/home/1-HowToSetup/esp/socs/xilinx-vc707-xc7vx485t/socketgen/noc_mlp3layers_hls4ml.vhd:111]
ERROR: [Synth 8-285] failed synthesizing module 'tile_acc' [/home/1-HowToSetup/esp/socs/xilinx-vc707-xc7vx485t/socketgen/tile_acc.vhd:98]
ERROR: [Synth 8-285] failed synthesizing module 'fpga_tile_acc' [/home/1-HowToSetup/esp/rtl/tiles/fpga/fpga_tile_acc.vhd:105]
ERROR: [Synth 8-285] failed synthesizing module 'esp' [/home/1-HowToSetup/esp/rtl/tiles/esp.vhd:65]
ERROR: [Synth 8-285] failed synthesizing module 'top' [/home/1-HowToSetup/esp/socs/xilinx-vc707-xc7vx485t/top.vhd:77]
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details

To Reproduce
Steps to reproduce the behavior:

1. https://www.esp.cs.columbia.edu/docs/hls4ml/hls4ml-guide/
2. Python 3.6.8
3. Board: xilinx-vc707-xc7vx485t

Expected behavior
After running make vivado-syn bit should be generated without errors including mlp3layers accelerator.

Desktop (please complete the following information):

• OS: [AlmaLinux 8.10 (Cerulean Leopard)]
• CAD tools versions: [vivado_hls 2019.2, soc desigh vivado 2023.2]

Additional context
Y would like to complete that tutorial and go forward implementing other keras models.