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HecaiYuanmr-c
HecaiYuan
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mr-c
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gcc loong64: work around the vec_perm_const bug in the LoongArch backend
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121064 has been fixed in the gcc-14 branch, and already released in gcc 15.2 Co-authored-by: Michael R. Crusoe <[email protected]>
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2 files changed

+15
-10
lines changed

2 files changed

+15
-10
lines changed

‎simde/arm/neon/ext.h‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -552,7 +552,7 @@ simde_vextq_f32(simde_float32x4_t a, simde_float32x4_t b, const int n)
552552
HEDLEY_STATIC_CAST(int8_t, ((n) + 2)), HEDLEY_STATIC_CAST(int8_t, ((n) + 3))); \
553553
simde_float32x4_from_private(simde_vextq_f32_r_); \
554554
}))
555-
#elif defined(SIMDE_SHUFFLE_VECTOR_) && !defined(SIMDE_ARM_NEON_A32V7_NATIVE) && !defined(SIMDE_BUG_GCC_BAD_VEXT_REV32)
555+
#elif defined(SIMDE_SHUFFLE_VECTOR_) && !defined(SIMDE_ARM_NEON_A32V7_NATIVE) && !defined(SIMDE_BUG_GCC_BAD_VEXT_REV32) && !defined(SIMDE_BUG_GCC_121064)
556556
#define simde_vextq_f32(a, b, n) (__extension__ ({ \
557557
simde_float32x4_private simde_vextq_f32_r_; \
558558
simde_vextq_f32_r_.values = SIMDE_SHUFFLE_VECTOR_(32, 16, simde_float32x4_to_private(a).values, simde_float32x4_to_private(b).values, \
@@ -656,7 +656,7 @@ simde_vextq_s8(simde_int8x16_t a, simde_int8x16_t b, const int n)
656656
HEDLEY_STATIC_CAST(int8_t, ((n) + 14)), HEDLEY_STATIC_CAST(int8_t, ((n) + 15))); \
657657
simde_int8x16_from_private(simde_vextq_s8_r_); \
658658
}))
659-
#elif defined(SIMDE_SHUFFLE_VECTOR_) && !defined(SIMDE_ARM_NEON_A32V7_NATIVE) && !defined(SIMDE_BUG_GCC_BAD_VEXT_REV32)
659+
#elif defined(SIMDE_SHUFFLE_VECTOR_) && !defined(SIMDE_ARM_NEON_A32V7_NATIVE) && !defined(SIMDE_BUG_GCC_BAD_VEXT_REV32) && !defined(SIMDE_BUG_GCC_121064)
660660
#define simde_vextq_s8(a, b, n) (__extension__ ({ \
661661
simde_int8x16_private simde_vextq_s8_r_; \
662662
simde_vextq_s8_r_.values = SIMDE_SHUFFLE_VECTOR_(8, 16, simde_int8x16_to_private(a).values, simde_int8x16_to_private(b).values, \
@@ -714,7 +714,7 @@ simde_vextq_s16(simde_int16x8_t a, simde_int16x8_t b, const int n)
714714
HEDLEY_STATIC_CAST(int8_t, ((n) + 6)), HEDLEY_STATIC_CAST(int8_t, ((n) + 7))); \
715715
simde_int16x8_from_private(simde_vextq_s16_r_); \
716716
}))
717-
#elif defined(SIMDE_SHUFFLE_VECTOR_) && !defined(SIMDE_ARM_NEON_A32V7_NATIVE) && !defined(SIMDE_BUG_GCC_BAD_VEXT_REV32)
717+
#elif defined(SIMDE_SHUFFLE_VECTOR_) && !defined(SIMDE_ARM_NEON_A32V7_NATIVE) && !defined(SIMDE_BUG_GCC_BAD_VEXT_REV32) && !defined(SIMDE_BUG_GCC_121064)
718718
#define simde_vextq_s16(a, b, n) (__extension__ ({ \
719719
simde_int16x8_private simde_vextq_s16_r_; \
720720
simde_vextq_s16_r_.values = SIMDE_SHUFFLE_VECTOR_(16, 16, simde_int16x8_to_private(a).values, simde_int16x8_to_private(b).values, \
@@ -766,7 +766,7 @@ simde_vextq_s32(simde_int32x4_t a, simde_int32x4_t b, const int n)
766766
HEDLEY_STATIC_CAST(int8_t, ((n) + 2)), HEDLEY_STATIC_CAST(int8_t, ((n) + 3))); \
767767
simde_int32x4_from_private(simde_vextq_s32_r_); \
768768
}))
769-
#elif defined(SIMDE_SHUFFLE_VECTOR_) && !defined(SIMDE_ARM_NEON_A32V7_NATIVE) && !defined(SIMDE_BUG_GCC_BAD_VEXT_REV32)
769+
#elif defined(SIMDE_SHUFFLE_VECTOR_) && !defined(SIMDE_ARM_NEON_A32V7_NATIVE) && !defined(SIMDE_BUG_GCC_BAD_VEXT_REV32) && !defined(SIMDE_BUG_GCC_121064)
770770
#define simde_vextq_s32(a, b, n) (__extension__ ({ \
771771
simde_int32x4_private simde_vextq_s32_r_; \
772772
simde_vextq_s32_r_.values = SIMDE_SHUFFLE_VECTOR_(32, 16, simde_int32x4_to_private(a).values, simde_int32x4_to_private(b).values, \
@@ -815,7 +815,7 @@ simde_vextq_s64(simde_int64x2_t a, simde_int64x2_t b, const int n)
815815
HEDLEY_STATIC_CAST(int8_t, ((n) + 0)), HEDLEY_STATIC_CAST(int8_t, ((n) + 1))); \
816816
simde_int64x2_from_private(simde_vextq_s64_r_); \
817817
}))
818-
#elif defined(SIMDE_SHUFFLE_VECTOR_) && !defined(SIMDE_ARM_NEON_A32V7_NATIVE) && !defined(SIMDE_BUG_GCC_BAD_VEXT_REV32)
818+
#elif defined(SIMDE_SHUFFLE_VECTOR_) && !defined(SIMDE_ARM_NEON_A32V7_NATIVE) && !defined(SIMDE_BUG_GCC_BAD_VEXT_REV32) && !defined(SIMDE_BUG_GCC_121064)
819819
#define simde_vextq_s64(a, b, n) (__extension__ ({ \
820820
simde_int64x2_private simde_vextq_s64_r_; \
821821
simde_vextq_s64_r_.values = SIMDE_SHUFFLE_VECTOR_(64, 16, simde_int64x2_to_private(a).values, simde_int64x2_to_private(b).values, \
@@ -856,7 +856,7 @@ simde_vextq_u8(simde_uint8x16_t a, simde_uint8x16_t b, const int n)
856856
}
857857
#if defined(SIMDE_X86_SSSE3_NATIVE) && !defined(SIMDE_BUG_GCC_SIZEOF_IMMEDIATE)
858858
#define simde_vextq_u8(a, b, n) simde_uint8x16_from_m128i(_mm_alignr_epi8(simde_uint8x16_to_m128i(b), simde_uint8x16_to_m128i(a), n * sizeof(uint8_t)))
859-
#elif defined(SIMDE_SHUFFLE_VECTOR_) && !defined(SIMDE_ARM_NEON_A32V7_NATIVE) && !defined(SIMDE_BUG_GCC_BAD_VEXT_REV32)
859+
#elif defined(SIMDE_SHUFFLE_VECTOR_) && !defined(SIMDE_ARM_NEON_A32V7_NATIVE) && !defined(SIMDE_BUG_GCC_BAD_VEXT_REV32) && !defined(SIMDE_BUG_GCC_121064)
860860
#define simde_vextq_u8(a, b, n) (__extension__ ({ \
861861
simde_uint8x16_private simde_vextq_u8_r_; \
862862
simde_vextq_u8_r_.values = SIMDE_SHUFFLE_VECTOR_(8, 16, simde_uint8x16_to_private(a).values, simde_uint8x16_to_private(b).values, \
@@ -904,7 +904,7 @@ simde_vextq_u16(simde_uint16x8_t a, simde_uint16x8_t b, const int n)
904904
}
905905
#if defined(SIMDE_X86_SSSE3_NATIVE) && !defined(SIMDE_BUG_GCC_SIZEOF_IMMEDIATE)
906906
#define simde_vextq_u16(a, b, n) simde_uint16x8_from_m128i(_mm_alignr_epi8(simde_uint16x8_to_m128i(b), simde_uint16x8_to_m128i(a), n * sizeof(uint16_t)))
907-
#elif defined(SIMDE_SHUFFLE_VECTOR_) && !defined(SIMDE_ARM_NEON_A32V7_NATIVE) && !defined(SIMDE_BUG_GCC_BAD_VEXT_REV32)
907+
#elif defined(SIMDE_SHUFFLE_VECTOR_) && !defined(SIMDE_ARM_NEON_A32V7_NATIVE) && !defined(SIMDE_BUG_GCC_BAD_VEXT_REV32) && !defined(SIMDE_BUG_GCC_121064)
908908
#define simde_vextq_u16(a, b, n) (__extension__ ({ \
909909
simde_uint16x8_private simde_vextq_u16_r_; \
910910
simde_vextq_u16_r_.values = SIMDE_SHUFFLE_VECTOR_(16, 16, simde_uint16x8_to_private(a).values, simde_uint16x8_to_private(b).values, \
@@ -914,7 +914,7 @@ simde_vextq_u16(simde_uint16x8_t a, simde_uint16x8_t b, const int n)
914914
HEDLEY_STATIC_CAST(int8_t, ((n) + 6)), HEDLEY_STATIC_CAST(int8_t, ((n) + 7))); \
915915
simde_uint16x8_from_private(simde_vextq_u16_r_); \
916916
}))
917-
#elif HEDLEY_HAS_BUILTIN(__builtin_shufflevector)
917+
#elif HEDLEY_HAS_BUILTIN(__builtin_shufflevector) && !defined(SIMDE_BUG_GCC_121064)
918918
#define simde_vextq_u16(a, b, n) (__extension__ ({ \
919919
simde_uint16x8_private r_; \
920920
r_.values = __builtin_shufflevector( \
@@ -957,7 +957,7 @@ simde_vextq_u32(simde_uint32x4_t a, simde_uint32x4_t b, const int n)
957957
}
958958
#if defined(SIMDE_X86_SSSE3_NATIVE) && !defined(SIMDE_BUG_GCC_SIZEOF_IMMEDIATE)
959959
#define simde_vextq_u32(a, b, n) simde_uint32x4_from_m128i(_mm_alignr_epi8(simde_uint32x4_to_m128i(b), simde_uint32x4_to_m128i(a), n * sizeof(uint32_t)))
960-
#elif defined(SIMDE_SHUFFLE_VECTOR_) && !defined(SIMDE_ARM_NEON_A32V7_NATIVE) && !defined(SIMDE_BUG_GCC_BAD_VEXT_REV32)
960+
#elif defined(SIMDE_SHUFFLE_VECTOR_) && !defined(SIMDE_ARM_NEON_A32V7_NATIVE) && !defined(SIMDE_BUG_GCC_BAD_VEXT_REV32) && !defined(SIMDE_BUG_GCC_121064)
961961
#define simde_vextq_u32(a, b, n) (__extension__ ({ \
962962
simde_uint32x4_private simde_vextq_u32_r_; \
963963
simde_vextq_u32_r_.values = SIMDE_SHUFFLE_VECTOR_(32, 16, simde_uint32x4_to_private(a).values, simde_uint32x4_to_private(b).values, \
@@ -999,7 +999,7 @@ simde_vextq_u64(simde_uint64x2_t a, simde_uint64x2_t b, const int n)
999999
}
10001000
#if defined(SIMDE_X86_SSSE3_NATIVE) && !defined(SIMDE_BUG_GCC_SIZEOF_IMMEDIATE)
10011001
#define simde_vextq_u64(a, b, n) simde_uint64x2_from_m128i(_mm_alignr_epi8(simde_uint64x2_to_m128i(b), simde_uint64x2_to_m128i(a), n * sizeof(uint64_t)))
1002-
#elif defined(SIMDE_SHUFFLE_VECTOR_) && !defined(SIMDE_ARM_NEON_A32V7_NATIVE) && !defined(SIMDE_BUG_GCC_BAD_VEXT_REV32)
1002+
#elif defined(SIMDE_SHUFFLE_VECTOR_) && !defined(SIMDE_ARM_NEON_A32V7_NATIVE) && !defined(SIMDE_BUG_GCC_BAD_VEXT_REV32) && !defined(SIMDE_BUG_GCC_121064)
10031003
#define simde_vextq_u64(a, b, n) (__extension__ ({ \
10041004
simde_uint64x2_private simde_vextq_u64_r_; \
10051005
simde_vextq_u64_r_.values = SIMDE_SHUFFLE_VECTOR_(64, 16, simde_uint64x2_to_private(a).values, simde_uint64x2_to_private(b).values, \

‎simde/simde-common.h‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1079,6 +1079,11 @@ HEDLEY_DIAGNOSTIC_POP
10791079
# if HEDLEY_GCC_VERSION_CHECK(16,0,0)
10801080
# define SIMDE_BUG_GCC_123807
10811081
# endif
1082+
# if defined(SIMDE_LOONGARCH_LSX_NATIVE) && \
1083+
((HEDLEY_GCC_VERSION_CHECK(14,0,0) && !HEDLEY_GCC_VERSION_CHECK(14,4,0)) || \
1084+
(HEDLEY_GCC_VERSION_CHECK(15,0,0) && !HEDLEY_GCC_VERSION_CHECK(15,2,0)))
1085+
# define SIMDE_BUG_GCC_121064
1086+
# endif
10821087
# endif
10831088
# if !defined(__OPTIMIZE__) && !(\
10841089
HEDLEY_GCC_VERSION_CHECK(11,4,0) \

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