[X86] Infinite Loop in type legalization when code generating extract.last.active

[huntergr-arm]

Given the following IR:

define i32 @foo(<4 x i32> %a, <4 x i1> %c) {
  %res = call i32 @llvm.experimental.vector.extract.last.active.v4i32(<4 x i32> %a, <4 x i1> %c, i32 -1)
  ret i32 %res
}

when generating code with llc -mtriple=x86_64-unknown-linux extract-last-active-test.ll we enter an infinite loop in type legalization:

Legalizing node: t104: i8 = extract_vector_elt t100, Constant:i64<0>
Analyzing result type: i8
Legal result type
Analyzing operand: t100: v4i8 = vselect t4, t94, t96
Widen node operand 0: t104: i8 = extract_vector_elt t100, Constant:i64<0>

Legalizing node: t104: i8 = extract_vector_elt t100, Constant:i64<0>
Analyzing result type: i8
Legal result type
Analyzing operand: t100: v4i8 = vselect t4, t94, t96
Widen node operand 0: t104: i8 = extract_vector_elt t100, Constant:i64<0>

Legalizing node: t104: i8 = extract_vector_elt t100, Constant:i64<0>
Analyzing result type: i8
Legal result type
Analyzing operand: t100: v4i8 = vselect t4, t94, t96
Widen node operand 0: t104: i8 = extract_vector_elt t100, Constant:i64<0>
.
.
.

This will succeed with -mattr=+avx512f.

See #158088 for reference.

[llvmbot]

@llvm/issue-subscribers-backend-x86

Author: Graham Hunter (huntergr-arm)

Given the following IR:

define i32 @<!-- -->foo(&lt;4 x i32&gt; %a, &lt;4 x i1&gt; %c) {
  %res = call i32 @<!-- -->llvm.experimental.vector.extract.last.active.v4i32(&lt;4 x i32&gt; %a, &lt;4 x i1&gt; %c, i32 -1)
  ret i32 %res
}

when generating code with llc -mtriple=x86_64-unknown-linux extract-last-active-test.ll we enter an infinite loop in type legalization:

Legalizing node: t104: i8 = extract_vector_elt t100, Constant:i64<0>
Analyzing result type: i8
Legal result type
Analyzing operand: t100: v4i8 = vselect t4, t94, t96
Widen node operand 0: t104: i8 = extract_vector_elt t100, Constant:i64<0>

Legalizing node: t104: i8 = extract_vector_elt t100, Constant:i64<0>
Analyzing result type: i8
Legal result type
Analyzing operand: t100: v4i8 = vselect t4, t94, t96
Widen node operand 0: t104: i8 = extract_vector_elt t100, Constant:i64<0>

Legalizing node: t104: i8 = extract_vector_elt t100, Constant:i64<0>
Analyzing result type: i8
Legal result type
Analyzing operand: t100: v4i8 = vselect t4, t94, t96
Widen node operand 0: t104: i8 = extract_vector_elt t100, Constant:i64<0>
.
.
.

This will succeed with -mattr=+avx512f.

See #158088 for reference.