[aarch64] Unnecessary masking of lower bits after ubfiz

[purplesyringa]

Godbolt

#include <stdint.h>

uint8_t f(uint8_t x, uint64_t n) {
    return (uint16_t)((x << 1) | (x << 8)) >> n;
}

f(unsigned char, unsigned long):
        ubfiz   w8, w0, #1, #8
        orr     w8, w8, w0, lsl #8
        and     w8, w8, #0xfffe ; why is this `and` here? `unfiz` should've zeroed the lowest bit
        lsr     w0, w8, w1
        ret

Happens during isel, not sure why.

[llvmbot]

@llvm/issue-subscribers-backend-aarch64

Author: Alisa Sireneva (purplesyringa)

[Godbolt](https://godbolt.org/z/oo6ocGK55)

#include <stdint.h>

uint8_t f(uint8_t x, uint64_t n) {
    return (uint16_t)((x << 1) | (x << 8)) >> n;
}

f(unsigned char, unsigned long):
        ubfiz   w8, w0, #<!-- -->1, #<!-- -->8
        orr     w8, w8, w0, lsl #<!-- -->8
        and     w8, w8, #<!-- -->0xfffe ; why is this `and` here?
        lsr     w0, w8, w1
        ret

Happens during isel, not sure why.

[davemgreen]

Hi. The top bits of w0 might not be 0, in the AArch64 PCS. If it was going to do this in 3 instructions it might need to reuse the result of the ubfiz and shift by a further 7 bits.

[cofibrant]

Hi. The top bits of w0 might not be 0, in the AArch64 PCS. If it was going to do this in 3 instructions it might need to reuse the result of the ubfiz and shift by a further 7 bits.

I'm not sure I follow... If we're worried about the upper bits of w0 being non-zero, why does the mask only zero out the lowest bit of w8?

Ah, sorry! I understand. This mask is zeroing out the top 2 bytes as well as the lowest bit. The fact that the compiler is using 0xfffe instead of 0xffff is just an artefact of a known-bits analysis spotting that the lsb is guaranteed to be 0.

[purplesyringa]

I see, I also missed that and masks out the highest bits (that's what you get for getting used to x86 "word" terminology). Thanks!

[davemgreen]

(Note that darwin will have a different PCS so make different assumptions about what needs to be cleared where. https://godbolt.org/z/xM7cnYPWG)