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[AArch64] Define apple-m5/a19 CPUs. (#171187)
A19 and M5 have been released in fall 2025. They add several features on top of M4/A18: - MTE, CSSC, HBC - SME2p1, SMEB16B16, SMEF16F16 - SPECRES2 This also bumps apple-latest to apple-m5.
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‎clang/test/Driver/print-enabled-extensions/aarch64-apple-m5.c‎

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// REQUIRES: aarch64-registered-target
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// RUN: %clang --target=aarch64 --print-enabled-extensions -mcpu=apple-m5 | FileCheck --strict-whitespace --implicit-check-not=FEAT_ %s
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// CHECK: Extensions enabled for the given AArch64 target
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// CHECK-EMPTY:
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// CHECK-NEXT: Architecture Feature(s) Description
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// CHECK-NEXT: FEAT_AES, FEAT_PMULL Enable AES support
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// CHECK-NEXT: FEAT_AMUv1 Enable Armv8.4-A Activity Monitors extension
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// CHECK-NEXT: FEAT_AMUv1p1 Enable Armv8.6-A Activity Monitors Virtualization support
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// CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions
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// CHECK-NEXT: FEAT_BF16 Enable BFloat16 Extension
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// CHECK-NEXT: FEAT_BTI Enable Branch Target Identification
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// CHECK-NEXT: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions
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// CHECK-NEXT: FEAT_CSSC Enable Common Short Sequence Compression (CSSC) instructions
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// CHECK-NEXT: FEAT_CSV2_2 Enable architectural speculation restriction
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// CHECK-NEXT: FEAT_DIT Enable Armv8.4-A Data Independent Timing instructions
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// CHECK-NEXT: FEAT_DPB Enable Armv8.2-A data Cache Clean to Point of Persistence
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// CHECK-NEXT: FEAT_DPB2 Enable Armv8.5-A Cache Clean to Point of Deep Persistence
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// CHECK-NEXT: FEAT_DotProd Enable dot product support
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// CHECK-NEXT: FEAT_ECV Enable enhanced counter virtualization extension
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// CHECK-NEXT: FEAT_FCMA Enable Armv8.3-A Floating-point complex number support
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// CHECK-NEXT: FEAT_FGT Enable fine grained virtualization traps extension
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// CHECK-NEXT: FEAT_FHM Enable FP16 FML instructions
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// CHECK-NEXT: FEAT_FP Enable Armv8.0-A Floating Point Extensions
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// CHECK-NEXT: FEAT_FP16 Enable half-precision floating-point data processing
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// CHECK-NEXT: FEAT_FPAC Enable Armv8.3-A Pointer Authentication Faulting enhancement
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// CHECK-NEXT: FEAT_FRINTTS Enable FRInt[32|64][Z|X] instructions that round a floating-point number to an integer (in FP format) forcing it to fit into a 32- or 64-bit int
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// CHECK-NEXT: FEAT_FlagM Enable Armv8.4-A Flag Manipulation instructions
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// CHECK-NEXT: FEAT_FlagM2 Enable alternative NZCV format for floating point comparisons
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// CHECK-NEXT: FEAT_HBC Enable Armv8.8-A Hinted Conditional Branches Extension
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// CHECK-NEXT: FEAT_HCX Enable Armv8.7-A HCRX_EL2 system register
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// CHECK-NEXT: FEAT_I8MM Enable Matrix Multiply Int8 Extension
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// CHECK-NEXT: FEAT_JSCVT Enable Armv8.3-A JavaScript FP conversion instructions
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// CHECK-NEXT: FEAT_LOR Enable Armv8.1-A Limited Ordering Regions extension
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// CHECK-NEXT: FEAT_LRCPC Enable support for RCPC extension
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// CHECK-NEXT: FEAT_LRCPC2 Enable Armv8.4-A RCPC instructions with Immediate Offsets
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// CHECK-NEXT: FEAT_LSE Enable Armv8.1-A Large System Extension (LSE) atomic instructions
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// CHECK-NEXT: FEAT_LSE2 Enable Armv8.4-A Large System Extension 2 (LSE2) atomicity rules
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// FIXME: Apple M5 does not have FEAT_MPAM, but it is currently marked as
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// non-optional in llvm's understanding of Armv8.4-A
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// CHECK-NEXT: FEAT_MPAM Enable Armv8.4-A Memory system Partitioning and Monitoring extension
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// CHECK-NEXT: FEAT_MTE, FEAT_MTE2 Enable Memory Tagging Extension
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// CHECK-NEXT: FEAT_NV, FEAT_NV2 Enable Armv8.4-A Nested Virtualization Enchancement
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// CHECK-NEXT: FEAT_PAN Enable Armv8.1-A Privileged Access-Never extension
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// CHECK-NEXT: FEAT_PAN2 Enable Armv8.2-A PAN s1e1R and s1e1W Variants
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// CHECK-NEXT: FEAT_PAuth Enable Armv8.3-A Pointer Authentication extension
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// CHECK-NEXT: FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension
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// CHECK-NEXT: FEAT_RAS, FEAT_RASv1p1 Enable Armv8.0-A Reliability, Availability and Serviceability Extensions
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// CHECK-NEXT: FEAT_RDM Enable Armv8.1-A Rounding Double Multiply Add/Subtract instructions
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// CHECK-NEXT: FEAT_SB Enable Armv8.5-A Speculation Barrier
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// FIXME: Apple M5 does not have FEAT_SEL2, but it is currently marked as
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// non-optional in llvm's understanding of Armv8.4-A
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// CHECK-NEXT: FEAT_SEL2 Enable Armv8.4-A Secure Exception Level 2 extension
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// CHECK-NEXT: FEAT_SHA1, FEAT_SHA256 Enable SHA1 and SHA256 support
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// CHECK-NEXT: FEAT_SHA3, FEAT_SHA512 Enable SHA512 and SHA3 support
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// CHECK-NEXT: FEAT_SME Enable Scalable Matrix Extension (SME)
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// CHECK-NEXT: FEAT_SME2 Enable Scalable Matrix Extension 2 (SME2) instructions
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// CHECK-NEXT: FEAT_SME2p1 Enable Scalable Matrix Extension 2.1 instructions
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// CHECK-NEXT: FEAT_SME_B16B16 Enable SME2.1 ZA-targeting non-widening BFloat16 instructions
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// CHECK-NEXT: FEAT_SME_F16F16 Enable SME non-widening Float16 instructions
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// CHECK-NEXT: FEAT_SME_F64F64 Enable Scalable Matrix Extension (SME) F64F64 instructions
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// CHECK-NEXT: FEAT_SME_I16I64 Enable Scalable Matrix Extension (SME) I16I64 instructions
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// CHECK-NEXT: FEAT_SPECRES Enable Armv8.5-A execution and data prediction invalidation instructions
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// CHECK-NEXT: FEAT_SPECRES2 Enable Speculation Restriction Instruction
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// CHECK-NEXT: FEAT_SVE_B16B16 Enable SVE2 non-widening and SME2 Z-targeting non-widening BFloat16 instructions
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// CHECK-NEXT: FEAT_TLBIOS, FEAT_TLBIRANGE Enable Armv8.4-A TLB Range and Maintenance instructions
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// CHECK-NEXT: FEAT_TRF Enable Armv8.4-A Trace extension
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// CHECK-NEXT: FEAT_UAO Enable Armv8.2-A UAO PState
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// CHECK-NEXT: FEAT_VHE Enable Armv8.1-A Virtual Host extension
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// CHECK-NEXT: FEAT_WFxT Enable Armv8.7-A WFET and WFIT instruction
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// CHECK-NEXT: FEAT_XS Enable Armv8.7-A limited-TLB-maintenance instruction

‎clang/test/Driver/print-supported-cpus-aarch64.c‎

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// CHECK: apple-a16
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// CHECK: apple-a17
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// CHECK: apple-a18
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// CHECK: apple-a19
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// CHECK: apple-a7
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// CHECK: apple-a8
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// CHECK: apple-a9
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// CHECK: apple-m1
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// CHECK: apple-m2
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// CHECK: apple-m3
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// CHECK: apple-m4
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// CHECK: apple-m5
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// CHECK: apple-s10
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// CHECK: apple-s4
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// CHECK: apple-s5

‎clang/test/Misc/target-invalid-cpu-note/aarch64.c‎

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// CHECK-SAME: {{^}}, apple-a16
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// CHECK-SAME: {{^}}, apple-a17
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// CHECK-SAME: {{^}}, apple-a18
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// CHECK-SAME: {{^}}, apple-a19
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// CHECK-SAME: {{^}}, apple-a7
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// CHECK-SAME: {{^}}, apple-a8
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// CHECK-SAME: {{^}}, apple-a9
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// CHECK-SAME: {{^}}, apple-m1
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// CHECK-SAME: {{^}}, apple-m2
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// CHECK-SAME: {{^}}, apple-m3
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// CHECK-SAME: {{^}}, apple-m4
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// CHECK-SAME: {{^}}, apple-m5
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// CHECK-SAME: {{^}}, apple-s10
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// CHECK-SAME: {{^}}, apple-s4
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// CHECK-SAME: {{^}}, apple-s5

‎llvm/lib/Target/AArch64/AArch64Processors.td‎

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@@ -517,6 +517,26 @@ def TuneAppleM4 : SubtargetFeature<"apple-m4", "ARMProcFamily", "AppleM4",
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FeatureNoZCZeroingFPR64,
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FeatureZCZeroingFPR128]>;
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def TuneAppleM5 : SubtargetFeature<"apple-m5", "ARMProcFamily", "AppleM5",
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"Apple M5", [
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FeatureAlternateSExtLoadCVTF32Pattern,
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FeatureArithmeticBccFusion,
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FeatureArithmeticCbzFusion,
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FeatureDisableLatencySchedHeuristic,
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FeatureFuseAddress,
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FeatureFuseAdrpAdd,
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FeatureFuseAES,
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FeatureFuseArithmeticLogic,
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FeatureFuseCmpCSel,
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FeatureFuseCryptoEOR,
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FeatureFuseLiterals,
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FeatureZCRegMoveGPR64,
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FeatureZCRegMoveFPR128,
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FeatureZCZeroingGPR32,
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FeatureZCZeroingGPR64,
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FeatureNoZCZeroingFPR64,
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FeatureZCZeroingFPR128]>;
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def TuneExynosM3 : SubtargetFeature<"exynosm3", "ARMProcFamily", "ExynosM3",
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"Samsung Exynos-M3 processors",
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[FeatureExynosCheapAsMoveHandling,
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FeatureLSE, FeaturePAuth, FeatureFPAC,
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FeatureRAS, FeatureRCPC, FeatureRDM,
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FeatureDotProd, FeatureMatMulInt8];
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list<SubtargetFeature> AppleM5 = [HasV8_7aOps, FeatureSHA2, FeatureFPARMv8,
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FeatureNEON, FeaturePerfMon, FeatureSHA3,
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FeatureFullFP16, FeatureFP16FML,
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FeatureAES, FeatureBF16,
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FeatureWFxT,
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FeatureSME, FeatureSME2,
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FeatureSMEF64F64, FeatureSMEI16I64,
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FeatureComplxNum, FeatureCRC, FeatureJS,
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FeatureLSE, FeaturePAuth, FeatureFPAC,
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FeatureRAS, FeatureRCPC, FeatureRDM,
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FeatureDotProd, FeatureMatMulInt8,
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FeatureMTE, FeatureCSSC, FeatureHBC,
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FeatureSME2p1, FeatureSMEB16B16, FeatureSMEF16F16,
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FeatureSPECRES2];
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list<SubtargetFeature> ExynosM3 = [HasV8_0aOps, FeatureCRC, FeatureSHA2, FeatureAES,
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FeaturePerfMon, FeatureNEON, FeatureFPARMv8];
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list<SubtargetFeature> ExynosM4 = [HasV8_2aOps, FeatureSHA2, FeatureAES, FeatureDotProd,
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[TuneAppleM4]>;
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def : ProcessorAlias<"apple-a18", "apple-m4">;
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def : ProcessorModel<"apple-m5", CycloneModel, ProcessorFeatures.AppleM5,
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[TuneAppleM5]>;
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def : ProcessorAlias<"apple-a19", "apple-m5">;
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// Alias for the latest Apple processor model supported by LLVM.
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def : ProcessorAlias<"apple-latest", "apple-m4">;
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def : ProcessorAlias<"apple-latest", "apple-m5">;
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// Fujitsu A64FX

‎llvm/lib/Target/AArch64/AArch64Subtarget.cpp‎

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@@ -218,6 +218,7 @@ void AArch64Subtarget::initializeProperties(bool HasMinSize) {
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case AppleA16:
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case AppleA17:
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case AppleM4:
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case AppleM5:
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CacheLineSize = 64;
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PrefetchDistance = 280;
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MinPrefetchStride = 2048;

‎llvm/lib/Target/AArch64/AArch64Subtarget.h‎

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case AppleA16:
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case AppleA17:
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case AppleM4:
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case AppleM5:
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return true;
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default:
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return false;

‎llvm/unittests/TargetParser/TargetParserTest.cpp‎

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@@ -1144,6 +1144,7 @@ INSTANTIATE_TEST_SUITE_P(
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AArch64CPUTestParams("apple-a17", "armv8.6-a"),
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AArch64CPUTestParams("apple-m4", "armv8.7-a"),
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AArch64CPUTestParams("apple-a18", "armv8.7-a"),
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AArch64CPUTestParams("apple-m5", "armv8.7-a"),
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AArch64CPUTestParams("exynos-m3", "armv8-a"),
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AArch64CPUTestParams("exynos-m4", "armv8.2-a"),
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AArch64CPUTestParams("exynos-m5", "armv8.2-a"),
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AArch64CPUAliasTestParams({"apple-a15", "apple-m2"}),
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AArch64CPUAliasTestParams({"apple-a16", "apple-m3",
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"apple-s9", "apple-s10"}),
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AArch64CPUAliasTestParams({"apple-m4", "apple-a18"})),
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AArch64CPUAliasTestParams({"apple-m4", "apple-a18"}),
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AArch64CPUAliasTestParams({"apple-m5", "apple-a19"})),
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AArch64CPUAliasTestParams::PrintToStringParamName);
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// Note: number of CPUs includes aliases.
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static constexpr unsigned NumAArch64CPUArchs = 91;
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static constexpr unsigned NumAArch64CPUArchs = 93;
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TEST(TargetParserTest, testAArch64CPUArchList) {
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SmallVector<StringRef, NumAArch64CPUArchs> List;

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