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1 | | -// RUN: mlir-opt %s -convert-amdgpu-to-rocdl=chipset=gfx942 | FileCheck %s |
2 | | -// RUN: mlir-opt %s -convert-amdgpu-to-rocdl=chipset=gfx950 | FileCheck %s |
| 1 | +// RUN: mlir-opt %s --convert-amdgpu-to-rocdl=chipset=gfx942 | FileCheck %s |
| 2 | +// RUN: mlir-opt %s --convert-amdgpu-to-rocdl=chipset=gfx950 | FileCheck %s |
3 | 3 |
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4 | 4 | #gpu_global_addrspace = 1 |
5 | 5 | #gpu_lds_addrspace = 3 |
@@ -43,6 +43,44 @@ func.func @global_load_to_rocdl_f32(%global : memref<128x72xf32, #gpu_global_add |
43 | 43 | func.return |
44 | 44 | } |
45 | 45 |
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| 46 | +// CHECK-LABEL: func @global_load_to_rocdl_wg_mem |
| 47 | +// CHECK-SAME: (%[[ARG0:.*]]: memref<128x72xf32>) |
| 48 | +func.func @global_load_to_rocdl_wg_mem(%global : memref<128x72xf32>) { |
| 49 | + %c0 = arith.constant 0 : index |
| 50 | + %c12 = arith.constant 12 : index |
| 51 | + %c32 = arith.constant 32 : index |
| 52 | + %alloc = memref.alloc() : memref<64x64xf32, #gpu.address_space<workgroup>> |
| 53 | + // CHECK: %[[GLOBAL_DESC:.*]] = builtin.unrealized_conversion_cast %[[ARG0]] |
| 54 | + |
| 55 | + // CHECK: %[[C0:.*]] = arith.constant 0 : index |
| 56 | + // CHECK: %[[IC0:.*]] = builtin.unrealized_conversion_cast %c0 : index to i64 |
| 57 | + // CHECK: %[[C12:.*]] = arith.constant 12 : index |
| 58 | + // CHECK: %[[IC12:.*]] = builtin.unrealized_conversion_cast %[[C12]] |
| 59 | + // CHECK: %[[C32:.*]] = arith.constant 32 : index |
| 60 | + // CHECK: %[[IC32:.*]] = builtin.unrealized_conversion_cast %[[C32]] |
| 61 | + |
| 62 | + // CHECK: %[[ALLOC:.*]] = memref.alloc() |
| 63 | + // CHECK: %[[LDS_DESC:.*]] = builtin.unrealized_conversion_cast |
| 64 | + // CHECK: %[[GLOBAL_BASE:.*]] = llvm.extractvalue %[[GLOBAL_DESC]][1] |
| 65 | + |
| 66 | + // CHECK: %[[C72:.*]] = llvm.mlir.constant(72 : index) : i64 |
| 67 | + // CHECK: %[[MUL:.*]] = llvm.mul %[[IC12]], %[[C72]] : i64 |
| 68 | + // CHECK: %[[SRC_OFFSET:.*]] = llvm.add %[[MUL]], %[[IC0]] : i64 |
| 69 | + |
| 70 | + // CHECK: %[[GLOBAL_PTR:.*]] = llvm.getelementptr %[[GLOBAL_BASE]][%[[SRC_OFFSET]]] |
| 71 | + // CHECK: %[[LDS_BASE:.*]] = llvm.extractvalue %[[LDS_DESC]][1] |
| 72 | + |
| 73 | + // CHECK: %[[C64:.*]] = llvm.mlir.constant(64 : index) : i64 |
| 74 | + // CHECK: %[[MUL_2:.*]] = llvm.mul %[[IC32]], %[[C64]] : i64 |
| 75 | + // CHECK: %[[DST_OFFSET:.*]] = llvm.add %[[MUL_2]], %[[IC0]] : i64 |
| 76 | + |
| 77 | + // CHECK: %[[LDS_PTR:.*]] = llvm.getelementptr %[[LDS_BASE]][%[[DST_OFFSET]]] |
| 78 | + // CHECK: rocdl.load.to.lds %[[GLOBAL_PTR]], %[[LDS_PTR]], 4 |
| 79 | + amdgpu.gather_to_lds %global[%c12, %c0], %alloc[%c32, %c0] |
| 80 | + : f32, memref<128x72xf32>, memref<64x64xf32, #gpu.address_space<workgroup>> |
| 81 | + func.return |
| 82 | +} |
| 83 | + |
46 | 84 | // CHECK-LABEL: func @global_load_to_rocdl_i8 |
47 | 85 | // CHECK-SAME: (%[[ARG0:.*]]: memref<128x72xi8, 1>) |
48 | 86 | func.func @global_load_to_rocdl_i8(%global : memref<128x72xi8, #gpu_global_addrspace>) { |
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