Skip to content

Commit 854ef8d

Browse files
vangthao95vangthao95
authored
[AMDGPU][GlobalISel] Add RegBankLegalize support for G_FSUB (#171244)
1 parent 9a727af commit 854ef8d

File tree

4 files changed

+232
-2
lines changed

4 files changed

+232
-2
lines changed

‎llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -948,6 +948,14 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
948948
hasSALUFloat)
949949
.Div(V2S16, {{VgprV2S16}, {VgprV2S16, VgprV2S16}});
950950

951+
addRulesForGOpcs({G_FSUB}, Standard)
952+
.Div(S16, {{Vgpr16}, {Vgpr16, Vgpr16}})
953+
.Div(S32, {{Vgpr32}, {Vgpr32, Vgpr32}})
954+
.Uni(S16, {{Sgpr16}, {Sgpr16, Sgpr16}}, hasSALUFloat)
955+
.Uni(S16, {{UniInVgprS16}, {Vgpr16, Vgpr16}}, !hasSALUFloat)
956+
.Uni(S32, {{Sgpr32}, {Sgpr32, Sgpr32}}, hasSALUFloat)
957+
.Uni(S32, {{UniInVgprS32}, {Vgpr32, Vgpr32}}, !hasSALUFloat);
958+
951959
// FNEG and FABS are either folded as source modifiers or can be selected as
952960
// bitwise XOR and AND with Mask. XOR and AND are available on SALU but for
953961
// targets without SALU float we still select them as VGPR since there would

‎llvm/test/CodeGen/AMDGPU/GlobalISel/fsub.ll‎

Lines changed: 220 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,220 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
2+
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mattr=-real-true16 -mcpu=gfx1100 -o - %s | FileCheck -check-prefixes=GCN,GFX11,GFX11-FAKE16 %s
3+
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mattr=+real-true16 -mcpu=gfx1100 -o - %s | FileCheck -check-prefixes=GCN,GFX11,GFX11-TRUE16 %s
4+
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mattr=-real-true16 -mcpu=gfx1200 -o - %s | FileCheck -check-prefixes=GCN,GFX12,GFX12-FAKE16 %s
5+
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mattr=+real-true16 -mcpu=gfx1200 -o - %s | FileCheck -check-prefixes=GCN,GFX12,GFX12-TRUE16 %s
6+
7+
define amdgpu_ps half @fsub_s16_uniform(half inreg %a, half inreg %b) {
8+
; GFX11-FAKE16-LABEL: fsub_s16_uniform:
9+
; GFX11-FAKE16: ; %bb.0:
10+
; GFX11-FAKE16-NEXT: v_sub_f16_e64 v0, s0, s1
11+
; GFX11-FAKE16-NEXT: ; return to shader part epilog
12+
;
13+
; GFX11-TRUE16-LABEL: fsub_s16_uniform:
14+
; GFX11-TRUE16: ; %bb.0:
15+
; GFX11-TRUE16-NEXT: v_sub_f16_e64 v0.l, s0, s1
16+
; GFX11-TRUE16-NEXT: ; return to shader part epilog
17+
;
18+
; GFX12-LABEL: fsub_s16_uniform:
19+
; GFX12: ; %bb.0:
20+
; GFX12-NEXT: s_sub_f16 s0, s0, s1
21+
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
22+
; GFX12-NEXT: v_mov_b32_e32 v0, s0
23+
; GFX12-NEXT: ; return to shader part epilog
24+
%fsub = fsub half %a, %b
25+
ret half %fsub
26+
}
27+
28+
define amdgpu_ps half @fsub_s16_div(half %a, half %b) {
29+
; GFX11-FAKE16-LABEL: fsub_s16_div:
30+
; GFX11-FAKE16: ; %bb.0:
31+
; GFX11-FAKE16-NEXT: v_sub_f16_e32 v0, v0, v1
32+
; GFX11-FAKE16-NEXT: ; return to shader part epilog
33+
;
34+
; GFX11-TRUE16-LABEL: fsub_s16_div:
35+
; GFX11-TRUE16: ; %bb.0:
36+
; GFX11-TRUE16-NEXT: v_sub_f16_e32 v0.l, v0.l, v1.l
37+
; GFX11-TRUE16-NEXT: ; return to shader part epilog
38+
;
39+
; GFX12-FAKE16-LABEL: fsub_s16_div:
40+
; GFX12-FAKE16: ; %bb.0:
41+
; GFX12-FAKE16-NEXT: v_sub_f16_e32 v0, v0, v1
42+
; GFX12-FAKE16-NEXT: ; return to shader part epilog
43+
;
44+
; GFX12-TRUE16-LABEL: fsub_s16_div:
45+
; GFX12-TRUE16: ; %bb.0:
46+
; GFX12-TRUE16-NEXT: v_sub_f16_e32 v0.l, v0.l, v1.l
47+
; GFX12-TRUE16-NEXT: ; return to shader part epilog
48+
%fsub = fsub half %a, %b
49+
ret half %fsub
50+
}
51+
52+
define amdgpu_ps float @fsub_s32_uniform(float inreg %a, float inreg %b) {
53+
; GFX11-LABEL: fsub_s32_uniform:
54+
; GFX11: ; %bb.0:
55+
; GFX11-NEXT: v_sub_f32_e64 v0, s0, s1
56+
; GFX11-NEXT: ; return to shader part epilog
57+
;
58+
; GFX12-LABEL: fsub_s32_uniform:
59+
; GFX12: ; %bb.0:
60+
; GFX12-NEXT: s_sub_f32 s0, s0, s1
61+
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
62+
; GFX12-NEXT: v_mov_b32_e32 v0, s0
63+
; GFX12-NEXT: ; return to shader part epilog
64+
%fsub = fsub float %a, %b
65+
ret float %fsub
66+
}
67+
68+
define amdgpu_ps float @fsub_s32_div(float %a, float %b) {
69+
; GCN-LABEL: fsub_s32_div:
70+
; GCN: ; %bb.0:
71+
; GCN-NEXT: v_sub_f32_e32 v0, v0, v1
72+
; GCN-NEXT: ; return to shader part epilog
73+
%fsub = fsub float %a, %b
74+
ret float %fsub
75+
}
76+
77+
define amdgpu_ps void @fsub_s64_uniform(double inreg %a, double inreg %b, ptr addrspace(1) %ptr) {
78+
; GFX11-LABEL: fsub_s64_uniform:
79+
; GFX11: ; %bb.0:
80+
; GFX11-NEXT: v_add_f64 v[2:3], s[0:1], -s[2:3]
81+
; GFX11-NEXT: global_store_b64 v[0:1], v[2:3], off
82+
; GFX11-NEXT: s_endpgm
83+
;
84+
; GFX12-LABEL: fsub_s64_uniform:
85+
; GFX12: ; %bb.0:
86+
; GFX12-NEXT: v_add_f64_e64 v[2:3], s[0:1], -s[2:3]
87+
; GFX12-NEXT: global_store_b64 v[0:1], v[2:3], off
88+
; GFX12-NEXT: s_endpgm
89+
%fsub = fsub double %a, %b
90+
store double %fsub, ptr addrspace(1) %ptr
91+
ret void
92+
}
93+
94+
define amdgpu_ps void @fsub_s64_div(double %a, double %b, ptr addrspace(1) %ptr) {
95+
; GFX11-LABEL: fsub_s64_div:
96+
; GFX11: ; %bb.0:
97+
; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], -v[2:3]
98+
; GFX11-NEXT: global_store_b64 v[4:5], v[0:1], off
99+
; GFX11-NEXT: s_endpgm
100+
;
101+
; GFX12-LABEL: fsub_s64_div:
102+
; GFX12: ; %bb.0:
103+
; GFX12-NEXT: v_add_f64_e64 v[0:1], v[0:1], -v[2:3]
104+
; GFX12-NEXT: global_store_b64 v[4:5], v[0:1], off
105+
; GFX12-NEXT: s_endpgm
106+
%fsub = fsub double %a, %b
107+
store double %fsub, ptr addrspace(1) %ptr
108+
ret void
109+
}
110+
111+
define amdgpu_ps <2 x half> @fsub_v2s16_uniform(<2 x half> inreg %a, <2 x half> inreg %b) {
112+
; GFX11-LABEL: fsub_v2s16_uniform:
113+
; GFX11: ; %bb.0:
114+
; GFX11-NEXT: v_pk_add_f16 v0, s0, s1 neg_lo:[0,1] neg_hi:[0,1]
115+
; GFX11-NEXT: ; return to shader part epilog
116+
;
117+
; GFX12-LABEL: fsub_v2s16_uniform:
118+
; GFX12: ; %bb.0:
119+
; GFX12-NEXT: s_lshr_b32 s2, s1, 16
120+
; GFX12-NEXT: s_xor_b32 s1, s1, 0x8000
121+
; GFX12-NEXT: s_xor_b32 s2, s2, 0x8000
122+
; GFX12-NEXT: s_lshr_b32 s3, s0, 16
123+
; GFX12-NEXT: s_add_f16 s0, s0, s1
124+
; GFX12-NEXT: s_add_f16 s1, s3, s2
125+
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_3) | instskip(NEXT) | instid1(SALU_CYCLE_1)
126+
; GFX12-NEXT: s_pack_ll_b32_b16 s0, s0, s1
127+
; GFX12-NEXT: v_mov_b32_e32 v0, s0
128+
; GFX12-NEXT: ; return to shader part epilog
129+
%fsub = fsub <2 x half> %a, %b
130+
ret <2 x half> %fsub
131+
}
132+
133+
define amdgpu_ps <2 x half> @fsub_v2s16_div(<2 x half> %a, <2 x half> %b) {
134+
; GCN-LABEL: fsub_v2s16_div:
135+
; GCN: ; %bb.0:
136+
; GCN-NEXT: v_pk_add_f16 v0, v0, v1 neg_lo:[0,1] neg_hi:[0,1]
137+
; GCN-NEXT: ; return to shader part epilog
138+
%fsub = fsub <2 x half> %a, %b
139+
ret <2 x half> %fsub
140+
}
141+
142+
define amdgpu_ps <2 x float> @fsub_v2s32_uniform(<2 x float> inreg %a, <2 x float> inreg %b) {
143+
; GFX11-LABEL: fsub_v2s32_uniform:
144+
; GFX11: ; %bb.0:
145+
; GFX11-NEXT: v_sub_f32_e64 v0, s0, s2
146+
; GFX11-NEXT: v_sub_f32_e64 v1, s1, s3
147+
; GFX11-NEXT: ; return to shader part epilog
148+
;
149+
; GFX12-LABEL: fsub_v2s32_uniform:
150+
; GFX12: ; %bb.0:
151+
; GFX12-NEXT: s_sub_f32 s0, s0, s2
152+
; GFX12-NEXT: s_sub_f32 s1, s1, s3
153+
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
154+
; GFX12-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
155+
; GFX12-NEXT: ; return to shader part epilog
156+
%fsub = fsub <2 x float> %a, %b
157+
ret <2 x float> %fsub
158+
}
159+
160+
define amdgpu_ps <2 x float> @fsub_v2s32_div(<2 x float> %a, <2 x float> %b) {
161+
; GCN-LABEL: fsub_v2s32_div:
162+
; GCN: ; %bb.0:
163+
; GCN-NEXT: v_dual_sub_f32 v0, v0, v2 :: v_dual_sub_f32 v1, v1, v3
164+
; GCN-NEXT: ; return to shader part epilog
165+
%fsub = fsub <2 x float> %a, %b
166+
ret <2 x float> %fsub
167+
}
168+
169+
define amdgpu_ps float @fsub_fneg_s32(float %a, float %b) {
170+
; GCN-LABEL: fsub_fneg_s32:
171+
; GCN: ; %bb.0:
172+
; GCN-NEXT: v_add_f32_e32 v0, v0, v1
173+
; GCN-NEXT: ; return to shader part epilog
174+
%neg = fneg float %b
175+
%result = fsub float %a, %neg
176+
ret float %result
177+
}
178+
179+
define amdgpu_ps float @fneg_fsub_s32(float %a, float %b) {
180+
; GCN-LABEL: fneg_fsub_s32:
181+
; GCN: ; %bb.0:
182+
; GCN-NEXT: v_sub_f32_e64 v0, -v0, v1
183+
; GCN-NEXT: ; return to shader part epilog
184+
%neg = fneg float %a
185+
%result = fsub float %neg, %b
186+
ret float %result
187+
}
188+
189+
define amdgpu_ps float @fsub_fabs_s32(float %a, float %b) {
190+
; GCN-LABEL: fsub_fabs_s32:
191+
; GCN: ; %bb.0:
192+
; GCN-NEXT: v_sub_f32_e64 v0, v0, |v1|
193+
; GCN-NEXT: ; return to shader part epilog
194+
%abs = call float @llvm.fabs.f32(float %b)
195+
%result = fsub float %a, %abs
196+
ret float %result
197+
}
198+
199+
define amdgpu_ps float @fabs_fsub_s32(float %a, float %b) {
200+
; GCN-LABEL: fabs_fsub_s32:
201+
; GCN: ; %bb.0:
202+
; GCN-NEXT: v_sub_f32_e64 v0, |v0|, v1
203+
; GCN-NEXT: ; return to shader part epilog
204+
%abs = call float @llvm.fabs.f32(float %a)
205+
%result = fsub float %abs, %b
206+
ret float %result
207+
}
208+
209+
define amdgpu_ps float @fsub_fneg_fabs_s32(float %a, float %b) {
210+
; GCN-LABEL: fsub_fneg_fabs_s32:
211+
; GCN: ; %bb.0:
212+
; GCN-NEXT: v_add_f32_e64 v0, v0, |v1|
213+
; GCN-NEXT: ; return to shader part epilog
214+
%abs = call float @llvm.fabs.f32(float %b)
215+
%neg = fneg float %abs
216+
%result = fsub float %a, %neg
217+
ret float %result
218+
}
219+
220+
declare float @llvm.fabs.f32(float)

‎llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fsub.mir‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2-
# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
3-
# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
2+
# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
3+
# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
44

55
---
66
name: fsub_ss

‎llvm/test/CodeGen/AMDGPU/fsub-as-fneg-src-modifier.ll‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2,6 +2,8 @@
22
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=CHECK,SDAG %s
33
; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=CHECK,GISEL %s
44

5+
; TODO: Switch test to use -new-reg-bank-select after adding G_FCANONICALIZE support.
6+
57
; Test that fneg is folded into source modifiers when it wasn't
68
; possible to fold fsub to fneg without context.
79

0 commit comments

Comments
 (0)