Optimize AVX2 Haswell DGEMM SUP Kernels for Improved FMA Throughput (#894)

Details:
- This commit enhances the performance of AVX2 DGEMM SUP edge kernels by addressing FMA instruction latency
  issues in low-computation scenarios, particularly in corner cases handled by edge kernels.
- Key Improvements:
  - Reduced FMA Latency:
    Previously, edge kernels reused a limited set of vector registers to hold FMA results, creating dependencies that 
    forced the CPU to wait for prior FMA instructions to complete before issuing new ones. This bottleneck was 
    especially pronounced in small-sized matrix multiplications.
  - Register Set Expansion:
    The updated implementation utilizes two distinct sets of vector registers to hold intermediate FMA results. 
    This allows subsequent FMA instructions to proceed without waiting for previous ones, improving 
    instruction-level parallelism and throughput.
  - Final Accumulation Strategy:
    At the end of the unrolled K-loop, the two register sets are summed to produce the final result, ensuring
     correctness while maintaining performance gains.
  - Modified Kernels:
    - m_left edge kernels:
      bli_dgemmsup_rv_haswell_asm_6x8m
      bli_dgemmsup_rv_haswell_asm_6x6m
      bli_dgemmsup_rv_haswell_asm_6x4m
      bli_dgemmsup_rv_haswell_asm_6x2m
    - mn_left edge kernels:
      bli_dgemmsup_rv_haswell_asm_{1..6}x{2,4,6,8}
  - Newly Added Kernels:
    - m_left kernels:
      bli_dgemmsup_rv_haswell_asm_6x{1,3,5,7}m
    - mn_left kernels:
      bli_dgemmsup_rv_haswell_asm_{1..6}x{1,3,5,7}
  These additions ensure comprehensive coverage for all edge-case matrix sizes, improving robustness
  and performance consistency across the DGEMM SUP microkernel suite.

Author: harsdave

frame/include/bli_x86_asm_macros.h

@@ -777,6 +777,7 @@
 #define VMOVDQA(_0, _1) INSTR_(vmovdqa, _0, _1)
 #define VMOVDQA32(_0, _1) INSTR_(vmovdqa32, _0, _1)
 #define VMOVDQA64(_0, _1) INSTR_(vmovdqa64, _0, _1)
+#define VMOVDQU(_0, _1) INSTR_(vmovdqu, _0, _1)
 #define VBROADCASTSS(_0, _1) INSTR_(vbroadcastss, _0, _1)
 #define VBROADCASTSD(_0, _1) INSTR_(vbroadcastsd, _0, _1)
 #define VPBROADCASTD(_0, _1) INSTR_(vpbroadcastd, _0, _1)
@@ -810,6 +811,7 @@
 #define vmovdqa(_0, _1) VMOVDQA(_0, _1)
 #define vmovdqa32(_0, _1) VMOVDQA32(_0, _1)
 #define vmovdqa64(_0, _1) VMOVDQA64(_0, _1)
+#define vmovdqu(_0, _1) VMOVDQU(_0, _1)
 #define vbroadcastss(_0, _1) VBROADCASTSS(_0, _1)
 #define vbroadcastsd(_0, _1) VBROADCASTSD(_0, _1)
 #define vpbroadcastd(_0, _1) VPBROADCASTD(_0, _1)
@@ -912,6 +914,8 @@
 #define VCOMISS(_0, _1) INSTR_(vcomiss, _0, _1)
 #define VCOMISD(_0, _1) INSTR_(vcomisd, _0, _1)
 
+#define VMASKMOVPD(_0, _1, _2) INSTR_(vmaskmovpd, _0, _1, _2)
+
 #define VFMADD132SS(_0, _1, _2) INSTR_(vfmadd132ss, _0, _1, _2)
 #define VFMADD213SS(_0, _1, _2) INSTR_(vfmadd213ss, _0, _1, _2)
 #define VFMADD231SS(_0, _1, _2) INSTR_(vfmadd231ss, _0, _1, _2)
@@ -1239,6 +1243,8 @@
 #define vblendmps(_0, _1, _2) VBLENDMSD(_0, _1, _2)
 #define vblendmpd(_0, _1, _2) VBLENDMPD(_0, _1, _2)
 
+#define vmaskmovpd(_0, _1, _2) VMASKMOVPD(_0, _1, _2)
+
 // Prefetches
 
 #define PREFETCH(_0, _1) INSTR_(prefetcht##_0, _1)