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| 1 | +// RUN: %clang -target xtensa -Wno-missing-multilib -x c -E -dM %s -o - | FileCheck -match-full-lines --check-prefix=CHECK-XTENSA %s |
| 2 | +// RUN: %clang -target xtensa-esp-unknown-elf -x c -E -dM %s -o - | FileCheck -match-full-lines --check-prefix=CHECK-XTENSA %s |
| 3 | +// CHECK-XTENSA: #define __XTENSA__ 1 |
| 4 | +// CHECK-XTENSA: #define __xtensa__ 1 |
| 5 | + |
| 6 | +// RUN: %clang -target xtensa-esp-unknown-elf -mcpu=esp32 -x c -E -dM %s -o - | FileCheck -match-full-lines --check-prefix=CHECK-ESP %s |
| 7 | +// RUN: %clang -target xtensa-esp-unknown-elf -mcpu=esp32s2 -x c -E -dM %s -o - | FileCheck -match-full-lines --check-prefix=CHECK-ESP %s |
| 8 | +// RUN: %clang -target xtensa-esp-unknown-elf -mcpu=esp32s3 -x c -E -dM %s -o - | FileCheck -match-full-lines --check-prefix=CHECK-ESP %s |
| 9 | +// CHECK-ESP: #define __XCHAL_DCACHE_IS_WRITEBACK 0 |
| 10 | +// CHECK-ESP: #define __XCHAL_DCACHE_LINESIZE 16 |
| 11 | +// CHECK-ESP: #define __XCHAL_DCACHE_LINEWIDTH 4 |
| 12 | +// CHECK-ESP: #define __XCHAL_DCACHE_SIZE 0 |
| 13 | +// CHECK-ESP: #define __XCHAL_DEBUGLEVEL 6 |
| 14 | +// CHECK-ESP: #define __XCHAL_HAVE_ABS 1 |
| 15 | +// CHECK-ESP: #define __XCHAL_HAVE_ADDX 1 |
| 16 | +// CHECK-ESP: #define __XCHAL_HAVE_BE 0 |
| 17 | +// CHECK-ESP: #define __XCHAL_HAVE_CONST16 0 |
| 18 | +// CHECK-ESP: #define __XCHAL_HAVE_DEBUG 1 |
| 19 | +// CHECK-ESP: #define __XCHAL_HAVE_DENSITY 1 |
| 20 | +// CHECK-ESP: #define __XCHAL_HAVE_DIV32 1 |
| 21 | +// CHECK-ESP: #define __XCHAL_HAVE_L32R 1 |
| 22 | +// CHECK-ESP: #define __XCHAL_HAVE_MINMAX 1 |
| 23 | +// CHECK-ESP: #define __XCHAL_HAVE_MMU 0 |
| 24 | +// CHECK-ESP: #define __XCHAL_HAVE_MUL16 1 |
| 25 | +// CHECK-ESP: #define __XCHAL_HAVE_MUL32 1 |
| 26 | +// CHECK-ESP: #define __XCHAL_HAVE_MUL32_HIGH 1 |
| 27 | +// CHECK-ESP: #define __XCHAL_HAVE_NSA 1 |
| 28 | +// CHECK-ESP: #define __XCHAL_HAVE_PREDICTED_BRANCHES 0 |
| 29 | +// CHECK-ESP: #define __XCHAL_HAVE_RELEASE_SYNC 1 |
| 30 | +// CHECK-ESP: #define __XCHAL_HAVE_SEXT 1 |
| 31 | +// CHECK-ESP: #define __XCHAL_HAVE_THREADPTR 1 |
| 32 | +// CHECK-ESP: #define __XCHAL_HAVE_WIDE_BRANCHES 0 |
| 33 | +// CHECK-ESP: #define __XCHAL_HAVE_WINDOWED 1 |
| 34 | +// CHECK-ESP: #define __XCHAL_ICACHE_LINESIZE 16 |
| 35 | +// CHECK-ESP: #define __XCHAL_ICACHE_LINEWIDTH 4 |
| 36 | +// CHECK-ESP: #define __XCHAL_ICACHE_SIZE 0 |
| 37 | +// CHECK-ESP: #define __XCHAL_INST_FETCH_WIDTH 4 |
| 38 | +// CHECK-ESP: #define __XCHAL_NUM_AREGS 64 |
| 39 | +// CHECK-ESP: #define __XCHAL_NUM_DBREAK 2 |
| 40 | +// CHECK-ESP: #define __XCHAL_NUM_IBREAK 2 |
| 41 | +// CHECK-ESP: #define __XTENSA_EL__ 1 |
| 42 | +// CHECK-ESP: #define __XTENSA_WINDOWED_ABI__ 1 |
| 43 | + |
| 44 | +// RUN: %clang -target xtensa-esp-unknown-elf -mcpu=esp32 -x c -E -dM %s -o - | FileCheck -match-full-lines --check-prefix=CHECK-ESP32_S3 %s |
| 45 | +// RUN: %clang -target xtensa-esp-unknown-elf -mcpu=esp32s3 -x c -E -dM %s -o - | FileCheck -match-full-lines --check-prefix=CHECK-ESP32_S3 %s |
| 46 | +// CHECK-ESP32_S3: #define __XCHAL_HAVE_BOOLEANS 1 |
| 47 | +// CHECK-ESP32_S3: #define __XCHAL_HAVE_FP 1 |
| 48 | +// CHECK-ESP32_S3: #define __XCHAL_HAVE_FP_DIV 1 |
| 49 | +// CHECK-ESP32_S3: #define __XCHAL_HAVE_FP_POSTINC 1 |
| 50 | +// CHECK-ESP32_S3: #define __XCHAL_HAVE_FP_RECIP 1 |
| 51 | +// CHECK-ESP32_S3: #define __XCHAL_HAVE_FP_RSQRT 1 |
| 52 | +// CHECK-ESP32_S3: #define __XCHAL_HAVE_FP_SQRT 1 |
| 53 | +// CHECK-ESP32_S3: #define __XCHAL_HAVE_LOOPS 1 |
| 54 | +// CHECK-ESP32_S3: #define __XCHAL_HAVE_MAC16 1 |
| 55 | +// CHECK-ESP32_S3: #define __XCHAL_HAVE_S32C1I 1 |
| 56 | + |
| 57 | +// RUN: %clang -target xtensa-esp-unknown-elf -mcpu=esp32 -x c -E -dM %s -o - | FileCheck -match-full-lines --check-prefix=CHECK-ESP32 %s |
| 58 | +// CHECK-ESP32: #define __XCHAL_HAVE_DFP_ACCEL 1 |
| 59 | +// CHECK-ESP32: #define __XCHAL_HAVE_DFP_DIV 1 |
| 60 | +// CHECK-ESP32: #define __XCHAL_HAVE_DFP_RECIP 1 |
| 61 | +// CHECK-ESP32: #define __XCHAL_HAVE_DFP_RSQRT 1 |
| 62 | +// CHECK-ESP32: #define __XCHAL_HAVE_DFP_SQRT 1 |
| 63 | +// CHECK-ESP32: #define __XCHAL_MAX_INSTRUCTION_SIZE 3 |
| 64 | + |
| 65 | +// RUN: %clang -target xtensa-esp-unknown-elf -mcpu=esp32s3 -x c -E -dM %s -o - | FileCheck -match-full-lines --check-prefix=CHECK-ESP32S3 %s |
| 66 | +// CHECK-ESP32S3: #define __XCHAL_HAVE_DFP_ACCEL 0 |
| 67 | +// CHECK-ESP32S3: #define __XCHAL_HAVE_DFP_DIV 0 |
| 68 | +// CHECK-ESP32S3: #define __XCHAL_HAVE_DFP_RECIP 0 |
| 69 | +// CHECK-ESP32S3: #define __XCHAL_HAVE_DFP_RSQRT 0 |
| 70 | +// CHECK-ESP32S3: #define __XCHAL_HAVE_DFP_SQRT 0 |
| 71 | +// CHECK-ESP32S3: #define __XCHAL_MAX_INSTRUCTION_SIZE 4 |
| 72 | + |
| 73 | +// RUN: %clang -target xtensa-esp-unknown-elf -mcpu=esp32s2 -x c -E -dM %s -o - | FileCheck -match-full-lines --check-prefix=CHECK-ESP32S2 %s |
| 74 | +// CHECK-ESP32S2: #define __XCHAL_HAVE_BOOLEANS 0 |
| 75 | +// CHECK-ESP32S2: #define __XCHAL_HAVE_DFP_ACCEL 0 |
| 76 | +// CHECK-ESP32S2: #define __XCHAL_HAVE_DFP_DIV 0 |
| 77 | +// CHECK-ESP32S2: #define __XCHAL_HAVE_DFP_RECIP 0 |
| 78 | +// CHECK-ESP32S2: #define __XCHAL_HAVE_DFP_RSQRT 0 |
| 79 | +// CHECK-ESP32S2: #define __XCHAL_HAVE_DFP_SQRT 0 |
| 80 | +// CHECK-ESP32S2: #define __XCHAL_HAVE_FP 0 |
| 81 | +// CHECK-ESP32S2: #define __XCHAL_HAVE_FP_DIV 0 |
| 82 | +// CHECK-ESP32S2: #define __XCHAL_HAVE_FP_POSTINC 0 |
| 83 | +// CHECK-ESP32S2: #define __XCHAL_HAVE_FP_RECIP 0 |
| 84 | +// CHECK-ESP32S2: #define __XCHAL_HAVE_FP_RSQRT 0 |
| 85 | +// CHECK-ESP32S2: #define __XCHAL_HAVE_FP_SQRT 0 |
| 86 | +// CHECK-ESP32S2: #define __XCHAL_HAVE_LOOPS 0 |
| 87 | +// CHECK-ESP32S2: #define __XCHAL_HAVE_MAC16 0 |
| 88 | +// CHECK-ESP32S2: #define __XCHAL_HAVE_S32C1I 0 |
| 89 | +// CHECK-ESP32S2: #define __XCHAL_MAX_INSTRUCTION_SIZE 3 |
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