[RISCV] Add user trap CSRs

Author: gerekon

llvm/lib/Target/RISCV/RISCVSystemOperands.td

@@ -327,6 +327,22 @@ let AltName = "dscratch" in
 def : SysReg<"dscratch0", 0x7B2>;
 def : SysReg<"dscratch1", 0x7B3>;
 
+//===----------------------------------------------------------------------===//
+// User Trap Setup
+//===----------------------------------------------------------------------===//
+def : SysReg<"ustatus", 0x000>;
+def : SysReg<"uie", 0x004>;
+def : SysReg<"utvec", 0x005>;
+
+//===----------------------------------------------------------------------===//
+// User Trap Handling
+//===----------------------------------------------------------------------===//
+def : SysReg<"uscratch", 0x040>;
+def : SysReg<"uepc", 0x041>;
+def : SysReg<"ucause", 0x042>;
+def : SysReg<"utval", 0x043>;
+def : SysReg<"uip", 0x044>;
+
 //===----------------------------------------------------------------------===//
 // User Vector CSRs
 //===----------------------------------------------------------------------===//

llvm/test/MC/RISCV/rv32e-valid.s

@@ -116,9 +116,9 @@ csrrw t0, 0xfff, t1
 csrrs s0, 0xc00, x0
 # CHECK-ASM-AND-OBJ: csrrs s0, fflags, a5
 csrrs s0, 0x001, a5
-# CHECK-ASM-AND-OBJ: csrrc sp, 0, ra
+# CHECK-ASM-AND-OBJ: csrrc sp, ustatus, ra
 csrrc sp, 0x000, ra
-# CHECK-ASM-AND-OBJ: csrrwi a5, 0, 0
+# CHECK-ASM-AND-OBJ: csrrwi a5, ustatus, 0
 csrrwi a5, 0x000, 0
 # CHECK-ASM-AND-OBJ: csrrsi t2, 4095, 31
 csrrsi t2, 0xfff, 31

llvm/test/MC/RISCV/rv32i-valid.s

@@ -361,10 +361,10 @@ csrrs s0, 0xc00, x0
 # CHECK-ASM-AND-OBJ: csrrs s3, fflags, s5
 # CHECK-ASM: encoding: [0xf3,0xa9,0x1a,0x00]
 csrrs s3, 0x001, s5
-# CHECK-ASM-AND-OBJ: csrrc sp, 0, ra
+# CHECK-ASM-AND-OBJ: csrrc sp, ustatus, ra
 # CHECK-ASM: encoding: [0x73,0xb1,0x00,0x00]
 csrrc sp, 0x000, ra
-# CHECK-ASM-AND-OBJ: csrrwi a5, 0, 0
+# CHECK-ASM-AND-OBJ: csrrwi a5, ustatus, 0
 # CHECK-ASM: encoding: [0xf3,0x57,0x00,0x00]
 csrrwi a5, 0x000, 0
 # CHECK-ASM-AND-OBJ: csrrsi t2, 4095, 31

llvm/test/MC/RISCV/user-csr-names.s

@@ -466,3 +466,119 @@ csrrs t2, 0xC1E, zero
 csrrs t1, hpmcounter31, zero
 # uimm12
 csrrs t2, 0xC1F, zero
+
+##################################
+# User Trap Setup
+##################################
+
+# ustatus
+# name
+# CHECK-INST: csrrs t1, ustatus, zero
+# CHECK-ENC:  encoding: [0x73,0x23,0x00,0x00]
+# CHECK-INST-ALIAS: csrr t1, ustatus
+# uimm12
+# CHECK-INST: csrrs t2, ustatus, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0x00,0x00]
+# CHECK-INST-ALIAS: csrr t2, ustatus
+# name
+csrrs t1, ustatus, zero
+# uimm12
+csrrs t2, 0x000, zero
+
+# uie
+# name
+# CHECK-INST: csrrs t1, uie, zero
+# CHECK-ENC:  encoding: [0x73,0x23,0x40,0x00]
+# CHECK-INST-ALIAS: csrr t1, uie
+# uimm12
+# CHECK-INST: csrrs t2, uie, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0x40,0x00]
+# CHECK-INST-ALIAS: csrr t2, uie
+# name
+csrrs t1, uie, zero
+# uimm12
+csrrs t2, 0x004, zero
+
+# utvec
+# name
+# CHECK-INST: csrrs t1, utvec, zero
+# CHECK-ENC:  encoding: [0x73,0x23,0x50,0x00]
+# CHECK-INST-ALIAS: csrr t1, utvec
+# uimm12
+# CHECK-INST: csrrs t2, utvec, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0x50,0x00]
+# CHECK-INST-ALIAS: csrr t2, utvec
+# name
+csrrs t1, utvec, zero
+# uimm12
+csrrs t2, 0x005, zero
+
+# uscratch
+# name
+# CHECK-INST: csrrs t1, uscratch, zero
+# CHECK-ENC:  encoding: [0x73,0x23,0x00,0x04]
+# CHECK-INST-ALIAS: csrr t1, uscratch
+# uimm12
+# CHECK-INST: csrrs t2, uscratch, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0x00,0x04]
+# CHECK-INST-ALIAS: csrr t2, uscratch
+# name
+csrrs t1, uscratch, zero
+# uimm12
+csrrs t2, 0x040, zero
+
+# uepc
+# name
+# CHECK-INST: csrrs t1, uepc, zero
+# CHECK-ENC:  encoding: [0x73,0x23,0x10,0x04]
+# CHECK-INST-ALIAS: csrr t1, uepc
+# uimm12
+# CHECK-INST: csrrs t2, uepc, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0x10,0x04]
+# CHECK-INST-ALIAS: csrr t2, uepc
+# name
+csrrs t1, uepc, zero
+# uimm12
+csrrs t2, 0x041, zero
+
+# ucause
+# name
+# CHECK-INST: csrrs t1, ucause, zero
+# CHECK-ENC:  encoding: [0x73,0x23,0x20,0x04]
+# CHECK-INST-ALIAS: csrr t1, ucause
+# uimm12
+# CHECK-INST: csrrs t2, ucause, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0x20,0x04]
+# CHECK-INST-ALIAS: csrr t2, ucause
+# name
+csrrs t1, ucause, zero
+# uimm12
+csrrs t2, 0x042, zero
+
+# utval
+# name
+# CHECK-INST: csrrs t1, utval, zero
+# CHECK-ENC:  encoding: [0x73,0x23,0x30,0x04]
+# CHECK-INST-ALIAS: csrr t1, utval
+# uimm12
+# CHECK-INST: csrrs t2, utval, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0x30,0x04]
+# CHECK-INST-ALIAS: csrr t2, utval
+# name
+csrrs t1, utval, zero
+# uimm12
+csrrs t2, 0x043, zero
+
+# uip
+# name
+# CHECK-INST: csrrs t1, uip, zero
+# CHECK-ENC:  encoding: [0x73,0x23,0x40,0x04]
+# CHECK-INST-ALIAS: csrr t1, uip
+# uimm12
+# CHECK-INST: csrrs t2, uip, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0x40,0x04]
+# CHECK-INST-ALIAS: csrr t2, uip
+# name
+csrrs t1, uip, zero
+# uimm12
+csrrs t2, 0x044, zero