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MabezDevandreisfr
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[Xtensa] Xtensa ABI 128bit arg alignment
- Forces 128bit arguments to have 128bit alignment as per the Xtensa ABI in LLVM & Clang. - Adds a check in the Xtensa calling convention to ensure 128bit aligned arguments are always passed as the first argument _or_ passed via the stack.
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3 files changed

+9
-4
lines changed

3 files changed

+9
-4
lines changed

clang/lib/Basic/Targets/Xtensa.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -50,7 +50,7 @@ class LLVM_LIBRARY_VISIBILITY XtensaTargetInfo : public TargetInfo {
5050
WIntType = UnsignedInt;
5151
UseZeroLengthBitfieldAlignment = true;
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MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
53-
resetDataLayout("e-m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32");
53+
resetDataLayout("e-m:e-p:32:32-i8:8:32-i16:16:32-i64:64-i128:128-n32");
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}
5555

5656
void getTargetDefines(const LangOptions &Opts,

llvm/lib/Target/Xtensa/XtensaISelLowering.cpp

Lines changed: 7 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -755,14 +755,19 @@ static bool CC_Xtensa_Custom(unsigned ValNo, MVT ValVT, MVT LocVT,
755755
unsigned Reg;
756756

757757
Align OrigAlign = ArgFlags.getNonZeroOrigAlign();
758-
bool isI64 = (ValVT == MVT::i32 && OrigAlign == Align(8));
758+
bool needs64BitAlign = (ValVT == MVT::i32 && OrigAlign == Align(8));
759+
bool needs128BitAlign = (ValVT == MVT::i32 && OrigAlign == Align(16));
759760

760761
if (ValVT == MVT::i32 || ValVT == MVT::f32) {
761762
Reg = State.AllocateReg(IntRegs);
762763
// If this is the first part of an i64 arg,
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// the allocated register must be either A2, A4 or A6.
764-
if (isI64 && (Reg == Xtensa::A3 || Reg == Xtensa::A5 || Reg == Xtensa::A7))
765+
if (needs64BitAlign && (Reg == Xtensa::A3 || Reg == Xtensa::A5 || Reg == Xtensa::A7))
765766
Reg = State.AllocateReg(IntRegs);
767+
// arguments with 16byte alignment must be passed in the first register or passed via stack
768+
if (needs128BitAlign && Reg != Xtensa::A2)
769+
while ( (Reg = State.AllocateReg(IntRegs)) ) {
770+
}
766771
LocVT = MVT::i32;
767772
} else if (ValVT == MVT::f64) {
768773
// Allocate int register and shadow next int register.

llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -33,7 +33,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeXtensaTarget() {
3333
static std::string computeDataLayout(const Triple &TT, StringRef CPU,
3434
const TargetOptions &Options,
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bool IsLittle) {
36-
std::string Ret = "e-m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32";
36+
std::string Ret = "e-m:e-p:32:32-i8:8:32-i16:16:32-i64:64-i128:128-n32";
3737

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return Ret;
3939
}

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