Improve port robustness, portability, and CSR handling

- replaced constants with named macros
- fixed TX_RESTORE logic to correctly clear/set bits
  and used read-modify-write patterns for mstatus.
- made some cleanups, formatting to better readability

Signed-off-by: Akif Ejaz <[email protected]>

Author: akifejaz

ports/risc-v64/gnu/inc/tx_port.h

@@ -71,6 +71,16 @@
 #endif
 #define REGBYTES (1 << LOG_REGBYTES)
 
+/* RISC-V mstatus bit definitions */
+#ifndef MSTATUS_MIE
+#define MSTATUS_MIE           (1UL << 3)    /* Machine interrupt enable */
+#define MSTATUS_MPIE          (1UL << 7)    /* Machine previous interrupt enable */
+#define MSTATUS_MPP_SHIFT     11
+#define MSTATUS_MPP_MASK      (3UL << MSTATUS_MPP_SHIFT)
+#define MSTATUS_MPP_MACHINE   (3UL << MSTATUS_MPP_SHIFT) /* MPP = Machine */
+#define MSTATUS_FS_INITIAL    (1UL << 13)   /* FP/FS state seed used by port */
+#endif
+
 #else   /*not __ASSEMBLER__ */
 
 /* Include for memset.  */
@@ -141,8 +151,13 @@ typedef unsigned short                          USHORT;
 
 /* Define various constants for the ThreadX RISC-V port.  */
 
-#define TX_INT_DISABLE                          0x00000000  /* Disable interrupts value */
-#define TX_INT_ENABLE                           0x00000008  /* Enable interrupt value   */
+/* This port assumes execution in Machine mode (M-mode). mstatus bits
+   are manipulated directly for interrupt control. For S-mode ports,
+   sstatus and SIE/SPIE semantics must be used instead. See the
+   RISC-V Privileged Spec for details. */
+
+#define TX_INT_DISABLE        0x00000000UL /* Disable interrupts value */
+#define TX_INT_ENABLE         MSTATUS_MIE  /* Enable interrupt value   */
 
 
 /* Define the clock source for trace event entry time stamp. The following two item are port specific.
@@ -253,23 +268,24 @@ typedef unsigned short                          USHORT;
    is used to define a local function save area for the disable and restore
    macros.  */
 
-#ifdef TX_DISABLE_INLINE
+/* Expose helper used to perform an atomic read/modify/write of mstatus.
+   The helper composes and returns the posture per ThreadX contract. */
+UINT                                            _tx_thread_interrupt_control(UINT new_posture);
 
-ULONG64                                         _tx_thread_interrupt_control(unsigned int new_posture);
+#ifdef TX_DISABLE_INLINE
 
-#define TX_INTERRUPT_SAVE_AREA                  register ULONG64 interrupt_save;
+#define TX_INTERRUPT_SAVE_AREA                  register UINT interrupt_save;
 
 #define TX_DISABLE                              interrupt_save =  _tx_thread_interrupt_control(TX_INT_DISABLE);
 #define TX_RESTORE                              _tx_thread_interrupt_control(interrupt_save);
 
 #else
 
-#define TX_INTERRUPT_SAVE_AREA                  ULONG64 interrupt_save;
-/* Atomically read mstatus into interrupt_save and clear bit 3 of mstatus.  */
-#define TX_DISABLE                              {__asm__ ("csrrci %0, mstatus, 0x08" : "=r" (interrupt_save) : );};
-/* We only care about mstatus.mie (bit 3), so mask interrupt_save and write to mstatus.  */
-#define TX_RESTORE                              {register ULONG64 __tempmask = interrupt_save & 0x08; \
-                                                __asm__ ("csrrs x0, mstatus, %0 \n\t" : : "r" (__tempmask) : );};
+/* Default inline macros delegate to the portable helper to ensure
+   correct read/modify/write semantics across toolchains. */
+#define TX_INTERRUPT_SAVE_AREA                  UINT interrupt_save;
+#define TX_DISABLE                              interrupt_save = _tx_thread_interrupt_control(TX_INT_DISABLE);
+#define TX_RESTORE                              _tx_thread_interrupt_control(interrupt_save);
 
 #endif