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diskounadiskouna
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Fix declaration hiding warning (Whide)
1 parent 10786d1 commit e966028

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3 files changed

+42
-42
lines changed

3 files changed

+42
-42
lines changed

‎tb/tb_apb4_booth_algorithm.vhd‎

Lines changed: 29 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -40,7 +40,7 @@ architecture behavioral of tb_apb4_booth_algorithm is
4040
signal booth_if_in, booth_if_out : booth_if_t;
4141

4242
-- BFM procedures
43-
procedure set_operands(signal clk : in std_logic;
43+
procedure set_operands(signal clk_p : in std_logic;
4444
signal core_if_out: in booth_if_t;
4545
signal core_if_in : out booth_if_t;
4646
constant a_value, b_value : in integer) is
@@ -49,13 +49,13 @@ architecture behavioral of tb_apb4_booth_algorithm is
4949
core_if_in.PSEL <= '1';
5050
-- Polling core ready flag
5151
while rdata(0) = '0' loop
52-
wait until rising_edge(clk); -- Setup phase
52+
wait until rising_edge(clk_p); -- Setup phase
5353
core_if_in.PENABLE <= '0';
5454
core_if_in.PADDR <= STAT_ADDR;
5555
core_if_in.PWRITE <= '0';
56-
wait until rising_edge(clk); -- Access phase
56+
wait until rising_edge(clk_p); -- Access phase
5757
core_if_in.PENABLE <= '1';
58-
wait until rising_edge(clk) and core_if_out.PREADY = '1';
58+
wait until rising_edge(clk_p) and core_if_out.PREADY = '1';
5959
rdata := core_if_out.PRDATA;
6060

6161
end loop;
@@ -64,50 +64,50 @@ architecture behavioral of tb_apb4_booth_algorithm is
6464
-- Setup phase
6565
core_if_in.PENABLE <= '0';
6666
core_if_in.PADDR <= OP_1_ADDR;
67-
core_if_in.PWDATA <= std_logic_vector(to_signed(a_value, core_if_in.PWDATA'length));
67+
core_if_in.PWDATA <= std_logic_vector(to_signed(a_value, core_if_in.PWDATA'length));
6868
core_if_in.PWRITE <= '1';
69-
wait until rising_edge(clk);
69+
wait until rising_edge(clk_p);
7070
-- Access phase
7171
core_if_in.PENABLE <= '1';
72-
wait until rising_edge(clk) and core_if_out.PREADY = '1';
72+
wait until rising_edge(clk_p) and core_if_out.PREADY = '1';
7373
core_if_in.PWRITE <= '0';
7474

7575
-- Write operand b
7676
-- Setup phase
77-
wait until rising_edge(clk);
77+
wait until rising_edge(clk_p);
7878
core_if_in.PENABLE <= '0';
7979
core_if_in.PADDR <= OP_2_ADDR;
80-
core_if_in.PWDATA <= std_logic_vector(to_signed(b_value, core_if_in.PWDATA'length));
80+
core_if_in.PWDATA <= std_logic_vector(to_signed(b_value, core_if_in.PWDATA'length));
8181
core_if_in.PWRITE <= '1';
82-
wait until rising_edge(clk);
82+
wait until rising_edge(clk_p);
8383
-- Access phase
8484
core_if_in.PENABLE <= '1';
85-
wait until rising_edge(clk) and core_if_out.PREADY = '1';
85+
wait until rising_edge(clk_p) and core_if_out.PREADY = '1';
8686
core_if_in.PWRITE <= '0';
8787

8888
-- Write operation enable flag
8989
-- Setup phase
90-
wait until rising_edge(clk);
90+
wait until rising_edge(clk_p);
9191
core_if_in.PENABLE <= '0';
9292
core_if_in.PADDR <= CTRL_ADDR;
93-
core_if_in.PWDATA <= x"0000_0001";
93+
core_if_in.PWDATA <= x"0000_0001";
9494
core_if_in.PWRITE <= '1';
95-
wait until rising_edge(clk);
95+
wait until rising_edge(clk_p);
9696
-- Access phase
9797
core_if_in.PENABLE <= '1';
98-
wait until rising_edge(clk) and core_if_out.PREADY = '1';
98+
wait until rising_edge(clk_p) and core_if_out.PREADY = '1';
9999
core_if_in.PWRITE <= '0';
100100

101-
wait until rising_edge(clk);
101+
wait until rising_edge(clk_p);
102102
core_if_in.PSEL <= '0';
103103
core_if_in.PENABLE <= '0';
104104
core_if_in.PWRITE <= '0';
105105

106106
report "Set a=" & integer'image(a_value) & " and b=" & integer'image(b_value)
107-
severity note;
108-
end procedure;
107+
severity note;
108+
end procedure;
109109

110-
procedure get_result(signal clk : in std_logic;
110+
procedure get_result(signal clk_p : in std_logic;
111111
signal core_if_out: in booth_if_t;
112112
signal core_if_in : out booth_if_t;
113113
variable c_value : out integer) is
@@ -117,36 +117,36 @@ architecture behavioral of tb_apb4_booth_algorithm is
117117
-- Polling result valid flag
118118
while core_if_out.PRDATA(1) = '0' loop
119119
-- Setup phase
120-
wait until rising_edge(clk);
120+
wait until rising_edge(clk_p);
121121
core_if_in.PENABLE <= '0';
122122
core_if_in.PADDR <= STAT_ADDR;
123123
core_if_in.PWRITE <= '0';
124-
wait until rising_edge(clk);
124+
wait until rising_edge(clk_p);
125125
-- Access phase
126126
core_if_in.PENABLE <= '1';
127-
wait until rising_edge(clk) and core_if_out.PREADY = '1';
127+
wait until rising_edge(clk_p) and core_if_out.PREADY = '1';
128128
end loop;
129129
-- Read overflow flag
130130
overflow := (core_if_out.PRDATA(2) = '1');
131131
-- Read result
132132
-- Setup phase
133-
wait until rising_edge(clk);
133+
wait until rising_edge(clk_p);
134134
core_if_in.PENABLE <= '0';
135135
core_if_in.PADDR <= RESULT_ADDR;
136136
core_if_in.PWRITE <= '0';
137-
wait until rising_edge(clk);
137+
wait until rising_edge(clk_p);
138138
-- Access phase
139139
core_if_in.PENABLE <= '1';
140-
wait until rising_edge(clk) and core_if_out.PREADY = '1';
140+
wait until rising_edge(clk_p) and core_if_out.PREADY = '1';
141141
c_value := to_integer(signed(core_if_out.PRDATA));
142142

143-
wait until rising_edge(clk);
143+
wait until rising_edge(clk_p);
144144
core_if_in.PSEL <= '0';
145145

146146
report "Got c=" & integer'image(to_integer(signed(core_if_out.PRDATA))) &
147147
" Overflow : " & boolean'image(overflow)
148-
severity note;
149-
end procedure;
148+
severity note;
149+
end procedure;
150150

151151
-- Checking procedure
152152
procedure check_result(constant result, expected_result : in integer;
@@ -184,7 +184,7 @@ begin
184184

185185
rstn <= '0';
186186
wait for 4 ns;
187-
rstn <= '1';
187+
rstn <= '1';
188188
report "Reset generation done" severity note;
189189

190190
-- Test case 1 : Two positive numbers

‎tb/tb_booth_algorithm.vhd‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -38,27 +38,27 @@ architecture behavioral of tb_booth_algorithm is
3838
signal booth_if_in, booth_if_out : booth_if_t;
3939

4040
-- BFM procedures
41-
procedure set_operands(signal clk : in std_logic;
41+
procedure set_operands(signal clk_p : in std_logic;
4242
signal core_if_out: in booth_if_t;
4343
signal core_if_in : out booth_if_t;
4444
constant a_value, b_value : in integer) is
4545
begin
4646
core_if_in.a_i <= std_logic_vector(to_signed(a_value, core_if_in.a_i'length));
4747
core_if_in.b_i <= std_logic_vector(to_signed(b_value, core_if_in.b_i'length));
4848
core_if_in.a_b_valid_i <= '1';
49-
wait until rising_edge(clk) and core_if_out.prod_ready_o = '1';
50-
wait until rising_edge(clk);
49+
wait until rising_edge(clk_p) and core_if_out.prod_ready_o = '1';
50+
wait until rising_edge(clk_p);
5151
core_if_in.a_b_valid_i <= '0';
5252
report "Set a=" & integer'image(a_value) & " and b=" & integer'image(b_value)
5353
severity note;
5454
end procedure;
5555

56-
procedure get_result(signal clk : in std_logic;
56+
procedure get_result(signal clk_p : in std_logic;
5757
signal core_if_out: in booth_if_t;
5858
signal core_if_in : out booth_if_t;
5959
variable c_value : out integer) is
6060
begin
61-
wait until rising_edge(clk) and core_if_out.c_valid_o = '1';
61+
wait until rising_edge(clk_p) and core_if_out.c_valid_o = '1';
6262
-- and core_if_in.cons_ready_i = '1' ;
6363
c_value := to_integer(signed(core_if_out.c_o));
6464
report "Got c=" & integer'image(to_integer(signed(core_if_out.c_o))) severity note;

‎tb/tb_reg_booth_algorithm.vhd‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -35,7 +35,7 @@ architecture behavioral of tb_reg_booth_algorithm is
3535
-- BFM procedures
3636

3737

38-
procedure set_operands(signal clk : in std_logic;
38+
procedure set_operands(signal clk_p : in std_logic;
3939
signal core_if_out: in booth_if_t;
4040
signal core_if_in : out booth_if_t;
4141
constant a_value, b_value : in integer) is
@@ -44,29 +44,29 @@ architecture behavioral of tb_reg_booth_algorithm is
4444
-- Read core ready flag
4545
core_if_in.we_i <= '0';
4646
core_if_in.addr_i <= STAT_ADDR;
47-
wait until rising_edge(clk) and core_if_out.rdata_o(0) = '1';
47+
wait until rising_edge(clk_p) and core_if_out.rdata_o(0) = '1';
4848
-- Write operand a
4949
core_if_in.addr_i <= OP_1_ADDR;
5050
core_if_in.wdata_i <= std_logic_vector(to_signed(a_value, core_if_in.wdata_i'length));
5151
core_if_in.we_i <= '1';
52-
wait until rising_edge(clk);
52+
wait until rising_edge(clk_p);
5353
-- Write operand b
5454
core_if_in.addr_i <= OP_2_ADDR;
5555
core_if_in.wdata_i <= std_logic_vector(to_signed(b_value, core_if_in.wdata_i'length));
5656
core_if_in.we_i <= '1';
57-
wait until rising_edge(clk);
57+
wait until rising_edge(clk_p);
5858
-- Write operation enable flag
5959
core_if_in.addr_i <= CTRL_ADDR;
6060
core_if_in.wdata_i <= x"0000_0001";
6161
core_if_in.we_i <= '1';
62-
wait until rising_edge(clk);
62+
wait until rising_edge(clk_p);
6363
core_if_in.sel_i <= '0';
6464

6565
report "Set a=" & integer'image(a_value) & " and b=" & integer'image(b_value)
6666
severity note;
6767
end procedure;
6868

69-
procedure get_result(signal clk : in std_logic;
69+
procedure get_result(signal clk_p : in std_logic;
7070
signal core_if_out: in booth_if_t;
7171
signal core_if_in : out booth_if_t;
7272
variable c_value : out integer) is
@@ -76,13 +76,13 @@ architecture behavioral of tb_reg_booth_algorithm is
7676
-- Read result valid flag
7777
core_if_in.we_i <= '0';
7878
core_if_in.addr_i <= STAT_ADDR;
79-
wait until rising_edge(clk) and core_if_out.rdata_o(1) = '1';
79+
wait until rising_edge(clk_p) and core_if_out.rdata_o(1) = '1';
8080
-- Read overflow flag
8181
overflow := (core_if_out.rdata_o(2) = '1');
8282
-- Read result
8383
core_if_in.we_i <= '0';
8484
core_if_in.addr_i <= RESULT_ADDR;
85-
wait until rising_edge(clk);
85+
wait until rising_edge(clk_p);
8686
c_value := to_integer(signed(core_if_out.rdata_o));
8787
core_if_in.sel_i <= '0';
8888

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