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feat[bsp][xuantie]: c/r serial cpus support SMP;
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‎.github/ALL_BSP_COMPILE.json‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -491,15 +491,15 @@
491491
"RTT_BSP": "xuantie",
492492
"RTT_TOOL_CHAIN": "sourcery-Xuantie-900-gcc-elf-newlib",
493493
"SUB_RTT_BSP": [
494-
"xuantie/smartl/e901",
494+
"xuantie/smartl/e901plus",
495495
"xuantie/smartl/e902",
496496
"xuantie/smartl/e906",
497497
"xuantie/smartl/e907",
498498
"xuantie/xiaohui/c906",
499499
"xuantie/xiaohui/c907",
500500
"xuantie/xiaohui/c908",
501501
"xuantie/xiaohui/c908x",
502-
"xuantie/xiaohui/c910",
502+
"xuantie/xiaohui/c920",
503503
"xuantie/xiaohui/r908",
504504
"xuantie/xiaohui/r910",
505505
"xuantie/xiaohui/r920"

‎bsp/README.md‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -773,14 +773,15 @@ This document is based on the RT-Thread mainline repository and categorizes the
773773

774774
| BSP Name | GPIO | UART | ADC | I2C | SPI | WDT |
775775
|----------|------|------|-----|-----|-----|-----|
776-
| [e901](xuantie/smartl/e901) | - | ✅ | - | - | - | - |
776+
| [e901plus](xuantie/smartl/e901plus) | - | ✅ | - | - | - | - |
777777
| [e902](xuantie/smartl/e902) | - | ✅ | - | - | - | - |
778778
| [e906](xuantie/smartl/e906) | - | ✅ | - | - | - | - |
779779
| [e907](xuantie/smartl/e907) | - | ✅ | - | - | - | - |
780780
| [c906 (RT-Smart)](xuantie/virt64/c906) | - | ✅ | - | - | - | - |
781781
| [c907](xuantie/xiaohui/c907) | - | ✅ | - | - | - | - |
782782
| [c908](xuantie/xiaohui/c908) | - | ✅ | - | - | - | - |
783-
| [c910](xuantie/xiaohui/c910) | - | ✅ | - | - | - | - |
783+
| [c908x](xuantie/xiaohui/c908x) | - | ✅ | - | - | - | - |
784+
| [c920](xuantie/xiaohui/c920) | - | ✅ | - | - | - | - |
784785
| [r908](xuantie/xiaohui/r908) | - | ✅ | - | - | - | - |
785786
| [r910](xuantie/xiaohui/r910) | - | ✅ | - | - | - | - |
786787
| [r920](xuantie/xiaohui/r920) | - | ✅ | - | - | - | - |

‎bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/gcc_flash_smartl.ld‎

Lines changed: 14 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -24,13 +24,13 @@
2424
******************************************************************************/
2525
MEMORY
2626
{
27-
ISRAM : ORIGIN = 0x00000000 , LENGTH = 0x20000 /* ISRAM 128KB*/
28-
DSRAM : ORIGIN = 0x20000000 , LENGTH = 0x80000 /* DSRAM 512KB*/
27+
ISRAM : ORIGIN = 0x00000000 , LENGTH = 0x30000 /* ISRAM 192KB*/
28+
DSRAM : ORIGIN = 0x20000000 , LENGTH = 0xC0000 /* DSRAM 768KB*/
2929
SRAM : ORIGIN = 0x60000000 , LENGTH = 0x20000 /* SRAM 128KB, no cacheable*/
3030
}
3131

3232
__min_heap_size = 0x200;
33-
PROVIDE (__ram_end = 0x20080000);
33+
PROVIDE (__ram_end = 0x200C0000);
3434
PROVIDE (__heap_end = __ram_end);
3535

3636
REGION_ALIAS("REGION_TEXT", ISRAM);
@@ -47,6 +47,7 @@ SECTIONS
4747
KEEP(*startup.o(*.text))
4848
KEEP(*startup.o(*.vectors))
4949
KEEP(*vectors.o(*.text))
50+
KEEP(*whetstone.o(*.text))
5051
KEEP(*(.text.entry))
5152
*(.text*)
5253
*(.gnu.warning)
@@ -64,6 +65,12 @@ SECTIONS
6465
. = ALIGN(0x10) ;
6566
__etext = . ;
6667
} > REGION_TEXT
68+
.eh_frame_hdr : {
69+
*(.eh_frame_hdr)
70+
} > REGION_TEXT
71+
.eh_frame : ONLY_IF_RO {
72+
KEEP (*(.eh_frame))
73+
} > REGION_TEXT
6774
.rodata : {
6875
. = ALIGN(0x4) ;
6976
__srodata = .;
@@ -189,7 +196,7 @@ SECTIONS
189196
KEEP(*(*.post_driver_entry))
190197
__post_driver_end__ = .;
191198
/************** end of drivers *********/
192-
. = ALIGN(0x4) ;
199+
. = ALIGN(0x8) ;
193200
__erodata = .;
194201
__rodata_end__ = .;
195202
} > REGION_RODATA
@@ -231,10 +238,10 @@ SECTIONS
231238
. = ALIGN(0x4) ;
232239
__ram_code_end__ = .;
233240
} > REGION_DATA AT > REGION_RODATA
234-
.bss : {
235-
. = ALIGN(0x4) ;
236-
__sbss = ALIGN(0x4) ;
241+
.bss : ALIGN(0x20) {
242+
__sbss = . ;
237243
__bss_start__ = . ;
244+
KEEP(*linpack.o(*.bss*))
238245
*(.dynsbss)
239246
*(.sbss)
240247
*(.sbss.*)

‎bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/include/asm/riscv_asm_macro.h‎

Lines changed: 28 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -25,26 +25,14 @@
2525
#ifndef __RISCV_ASM_MACRO_H__
2626
#define __RISCV_ASM_MACRO_H__
2727

28-
#if (!defined(__riscv_flen)) && (CONFIG_CHECK_FPU_DIRTY)
29-
#error "this cpu doesn't supprot FPU, but macro 'CONFIG_CHECK_FPU_DIRTY' is defined, please remove it."
30-
#endif
31-
32-
#if (!defined(__riscv_vector)) && (CONFIG_CHECK_VECTOR_DIRTY)
33-
#error "this cpu doesn't supprot vector, but macro 'CONFIG_CHECK_VECTOR_DIRTY' is defined, please remove it."
34-
#endif
35-
36-
#if (!defined(__riscv_matrix) && !defined(__riscv_xtheadmatrix)) && (CONFIG_CHECK_MATRIX_DIRTY)
37-
#error "this cpu doesn't supprot matrix, but macro 'CONFIG_CHECK_MATRIX_DIRTY' is defined, please remove it."
38-
#endif
39-
28+
#include <rtconfig.h>
4029
#include "riscv_csr.h"
4130

42-
#if CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY
4331
.macro RESTORE_MSTATUS
4432
/* t0 and t1 are not restored before using */
4533
/* now, sp is at the top of the stack (the lowest address)*/
4634
li t1, 0
47-
#if __riscv_matrix || __riscv_xtheadmatrix /* matrix registers */
35+
#if (__riscv_matrix || __riscv_xtheadmatrix) && defined(ARCH_RISCV_MATRIX) /* matrix registers */
4836
#if __riscv_xlen == 64
4937
addi t1, t1, (12 + 12)
5038
#else
@@ -55,7 +43,7 @@
5543
add t1, t1, t0
5644
#endif /* __riscv_matrix || __riscv_xtheadmatrix */
5745

58-
#ifdef __riscv_vector /* vector registers */
46+
#if __riscv_vector && defined(ARCH_RISCV_VECTOR) /* vector registers */
5947
csrr t0, vlenb
6048
slli t0, t0, 5
6149
add t1, t1, t0
@@ -66,6 +54,7 @@
6654
#endif /* __riscv_xlen */
6755
#endif /* __riscv_vector */
6856

57+
#if __riscv_flen && defined(ARCH_RISCV_FPU)
6958
#if __riscv_flen == 64 /* float registers */
7059
#if __riscv_xlen == 64
7160
addi t1, t1, 168
@@ -76,8 +65,9 @@
7665
#elif __riscv_flen == 32
7766
addi t1, t1, 84
7867
#endif /* __riscv_flen */
68+
#endif
7969

80-
#ifdef __riscv_dsp /* vxsat register, 32-bit cpu only */
70+
#if __riscv_dsp && defined(ARCH_RISCV_DSP) /* vxsat register, 32-bit cpu only */
8171
addi t1, t1, 4
8272
#endif /* __riscv_dsp */
8373

@@ -86,19 +76,18 @@
8676
#elif __riscv_xlen == 32
8777
addi t1, t1, 72
8878
#endif
89-
add sp, sp, t1
79+
add t1, sp, t1
9080

91-
/* now, sp is the position of mstatus */
92-
load_x t3, (0)(sp)
81+
/* now, t1 is the position of mstatus */
82+
load_x t3, (0)(t1)
9383
csrw mstatus, t3
94-
sub sp, sp, t1
9584
.endm
9685

9786
.macro RESTORE_SSTATUS
9887
/* t0 and t1 are not restored before using */
9988
/* now, sp is at the top of the stack (the lowest address)*/
10089
li t1, 0
101-
#if __riscv_matrix || __riscv_xtheadmatrix /* matrix registers */
90+
#if (__riscv_matrix || __riscv_xtheadmatrix) && defined(ARCH_RISCV_MATRIX) /* matrix registers */
10291
#if __riscv_xlen == 64
10392
addi t1, t1, (12 + 12)
10493
#else
@@ -109,7 +98,7 @@
10998
add t1, t1, t0
11099
#endif /* __riscv_matrix || __riscv_xtheadmatrix */
111100

112-
#ifdef __riscv_vector /* vector registers */
101+
#if __riscv_vector && defined(ARCH_RISCV_VECTOR) /* vector registers */
113102
csrr t0, vlenb
114103
slli t0, t0, 5
115104
add t1, t1, t0
@@ -120,6 +109,7 @@
120109
#endif /* __riscv_xlen */
121110
#endif /* __riscv_vector */
122111

112+
#if __riscv_flen && defined(ARCH_RISCV_FPU)
123113
#if __riscv_flen == 64 /* float registers */
124114
#if __riscv_xlen == 64
125115
addi t1, t1, 168
@@ -130,26 +120,24 @@
130120
#elif __riscv_flen == 32
131121
addi t1, t1, 84
132122
#endif /* __riscv_flen */
123+
#endif
133124

134125
#if __riscv_xlen == 64 /*general purpose registers*/
135126
addi t1, t1, (72 + 72)
136127
#elif __riscv_xlen == 32
137128
addi t1, t1, 72
138129
#endif
139-
add sp, sp, t1
130+
add t1, sp, t1
140131

141-
/* now, sp is the position of mstatus */
142-
load_x t3, (0)(sp)
132+
/* now, t1 is the position of mstatus */
133+
load_x t3, (0)(t1)
143134
csrw sstatus, t3
144-
sub sp, sp, t1
145135
.endm
146136

147-
#endif /* CONFIG_CHECK_FPU_DIRTY || CONFIG_CHECK_VECTOR_DIRTY || CONFIG_CHECK_MATRIX_DIRTY */
148-
149137
.macro SAVE_VECTOR_REGISTERS
150138
/* t0,t1 saved before using */
151139
/* mstatus->t3 */
152-
#ifdef __riscv_vector
140+
#if __riscv_vector && defined(ARCH_RISCV_VECTOR)
153141
#if CONFIG_CHECK_VECTOR_DIRTY
154142
/* check if VS filed of MSTATUS is 'dirty' */
155143
li t1, SR_VS_DIRTY
@@ -227,7 +215,7 @@
227215

228216
.macro RESTORE_VECTOR_REGISTERS
229217
/* t0,t1,t2 not restored before using, mstatus has been restored before using */
230-
#ifdef __riscv_vector
218+
#if __riscv_vector && defined(ARCH_RISCV_VECTOR)
231219
#if CONFIG_CHECK_VECTOR_DIRTY
232220
/* check if VS filed of MSTATUS is 'dirty' */
233221
li t1, SR_VS_DIRTY
@@ -304,6 +292,7 @@
304292

305293
.macro SAVE_FLOAT_REGISTERS
306294
/* t0, t1 saved before using */
295+
#if __riscv_flen && defined(ARCH_RISCV_FPU)
307296
#if __riscv_flen == 64
308297
#if CONFIG_CHECK_FPU_DIRTY
309298
/* check if FS filed of MSTATUS is 'dirty' */
@@ -378,10 +367,12 @@
378367
fstore_x ft10,72(sp)
379368
fstore_x ft11,76(sp)
380369
#endif /*__riscv_flen */
370+
#endif
381371
#if CONFIG_CHECK_FPU_DIRTY
382372
j 2f
383373
1:
384374
/* don't store, move sp only */
375+
#if __riscv_flen && defined(ARCH_RISCV_FPU)
385376
#if __riscv_flen == 64
386377
#if __riscv_xlen == 64
387378
addi sp, sp, -168
@@ -391,12 +382,14 @@
391382
#elif __riscv_flen == 32
392383
addi sp, sp, -84
393384
#endif /* __riscv_xlen */
385+
#endif
394386
2:
395387
#endif
396388
.endm
397389

398390
.macro RESTORE_FLOAT_REGISTERS
399391
/* t0 and t1 are not restored before using, mstatus has been restored before using */
392+
#if __riscv_flen && defined(ARCH_RISCV_FPU)
400393
#if __riscv_flen == 64
401394
#if CONFIG_CHECK_FPU_DIRTY
402395
/* check if FS filed of MSTATUS is 'dirty' */
@@ -472,10 +465,12 @@
472465
fscsr t0
473466
addi sp, sp, 4
474467
#endif /*__riscv_flen */
468+
#endif
475469
#if CONFIG_CHECK_FPU_DIRTY
476470
j 2f
477471
1:
478472
/* don't restore, move sp only */
473+
#if __riscv_flen && defined(ARCH_RISCV_FPU)
479474
#if __riscv_flen == 64
480475
#if __riscv_xlen == 64
481476
addi sp, sp, 168
@@ -485,14 +480,15 @@
485480
#elif __riscv_flen == 32
486481
addi sp, sp, 84
487482
#endif /* __riscv_flen */
483+
#endif
488484
2:
489485
#endif /* CONFIG_CHECK_FPU_DIRTY */
490486
.endm
491487

492488
.macro SAVE_MATRIX_REGISTERS
493489
/* t0,t1 saved before using */
494490

495-
#if __riscv_matrix || __riscv_xtheadmatrix
491+
#if (__riscv_matrix || __riscv_xtheadmatrix) && defined(ARCH_RISCV_MATRIX)
496492
#if CONFIG_CHECK_MATRIX_DIRTY
497493
/* check if FS filed of MSTATUS is 'dirty' */
498494
li t1, SR_MS_DIRTY
@@ -544,7 +540,7 @@
544540
.macro RESTORE_MATRIX_REGISTERS
545541
/* t0 and t1 are not restored before using, mstatus has been restored before using */
546542

547-
#if __riscv_matrix || __riscv_xtheadmatrix
543+
#if (__riscv_matrix || __riscv_xtheadmatrix) && defined(ARCH_RISCV_MATRIX)
548544
#if CONFIG_CHECK_MATRIX_DIRTY
549545
/* check if FS filed of MSTATUS is 'dirty' */
550546
li t1, SR_MS_DIRTY

‎bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/include/asm/riscv_csr.h‎

Lines changed: 15 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -69,7 +69,9 @@
6969
#define SR_FS_CLEAN 0x00004000UL
7070
#define SR_FS_DIRTY 0x00006000UL
7171

72-
#if CONFIG_CPU_XUANTIE_C906 || CONFIG_CPU_XUANTIE_C906FD || CONFIG_CPU_XUANTIE_C906FDV || CONFIG_CPU_XUANTIE_R920
72+
#if CONFIG_CPU_XUANTIE_C906 || CONFIG_CPU_XUANTIE_C906FD || CONFIG_CPU_XUANTIE_C906FDV \
73+
|| CONFIG_CPU_XUANTIE_R920 \
74+
|| CONFIG_CPU_XUANTIE_C920
7375
#define SR_VS 0x01800000
7476
#define SR_VS_OFF 0x00000000
7577
#define SR_VS_INITIAL 0x00800000
@@ -128,17 +130,26 @@
128130
#define MSTATUS_MPP_SHIFT 11
129131
#define MSTATUS_MPP (3 << MSTATUS_MPP_SHIFT)
130132

131-
#if CONFIG_CPU_XUANTIE_C906 || CONFIG_CPU_XUANTIE_C906FD || CONFIG_CPU_XUANTIE_C906FDV || CONFIG_CPU_XUANTIE_R910 || CONFIG_CPU_XUANTIE_R920
133+
#if CONFIG_CPU_XUANTIE_C906 || CONFIG_CPU_XUANTIE_C906FD || CONFIG_CPU_XUANTIE_C906FDV \
134+
|| CONFIG_CPU_XUANTIE_R910 || CONFIG_CPU_XUANTIE_R920 \
135+
|| CONFIG_CPU_XUANTIE_C910 || CONFIG_CPU_XUANTIE_C920
132136
#define MSTATUS_VS_SHIFT 23
133137
#else
134138
#define MSTATUS_VS_SHIFT 9
135139
#endif
136140
#define MSTATUS_FS_SHIFT 13
137141
#define MSTATUS_MS_SHIFT 25
138142

139-
#define INSERT_FIELD(val, which, fieldval) (((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1))))
143+
#define INSERT_FIELD(val, which, fieldval) (((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1))))
140144

141-
#if CONFIG_CPU_XUANTIE_C906 || CONFIG_CPU_XUANTIE_C906FD || CONFIG_CPU_XUANTIE_C906FDV || CONFIG_CPU_XUANTIE_C908 || CONFIG_CPU_XUANTIE_C908V ||CONFIG_CPU_XUANTIE_C908I || CONFIG_CPU_XUANTIE_R910 || CONFIG_CPU_XUANTIE_R920
145+
#if CONFIG_CPU_XUANTIE_C906 || CONFIG_CPU_XUANTIE_C906FD || CONFIG_CPU_XUANTIE_C906FDV \
146+
|| CONFIG_CPU_XUANTIE_C908 || CONFIG_CPU_XUANTIE_C908V || CONFIG_CPU_XUANTIE_C908I \
147+
|| CONFIG_CPU_XUANTIE_C908_V2 || CONFIG_CPU_XUANTIE_C908V_V2 || CONFIG_CPU_XUANTIE_C908I_V2 \
148+
|| CONFIG_CPU_XUANTIE_C908_CP_V2 || CONFIG_CPU_XUANTIE_C908V_CP_V2 || CONFIG_CPU_XUANTIE_C908I_CP_V2 \
149+
|| CONFIG_CPU_XUANTIE_C908_CP_XT_V2 || CONFIG_CPU_XUANTIE_C908V_CP_XT_V2 || CONFIG_CPU_XUANTIE_C908I_CP_XT_V2 \
150+
|| CONFIG_CPU_XUANTIE_C908VK_CP_V2 || CONFIG_CPU_XUANTIE_C908VK_CP_XT_V2 \
151+
|| CONFIG_CPU_XUANTIE_R910 || CONFIG_CPU_XUANTIE_R920 \
152+
|| CONFIG_CPU_XUANTIE_C910 || CONFIG_CPU_XUANTIE_C920
142153
#define ATTR_SO (1ull << 4)
143154
#define ATTR_CA (1ull << 3)
144155
#define ATTR_BU (1ull << 2)

‎bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/include/csi_config.h‎

Lines changed: 27 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,27 @@
1+
/*
2+
* Copyright (C) 2017-2024 Alibaba Group Holding Limited
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*
6+
* Licensed under the Apache License, Version 2.0 (the "License");
7+
* you may not use this file except in compliance with the License.
8+
* You may obtain a copy of the License at
9+
*
10+
* http://www.apache.org/licenses/LICENSE-2.0
11+
*
12+
* Unless required by applicable law or agreed to in writing, software
13+
* distributed under the License is distributed on an "AS IS" BASIS,
14+
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15+
* See the License for the specific language governing permissions and
16+
* limitations under the License.
17+
*/
18+
19+
#ifndef __CSI_CONFIG_H__
20+
#define __CSI_CONFIG_H__
21+
22+
#if CONFIG_KERNEL_RTTHREAD
23+
#include <rtconfig.h>
24+
#endif
25+
26+
27+
#endif /* end of __CSI_CONFIG_H__ */

bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c906fd/SConscript renamed to bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/c906/SConscript

File renamed without changes.

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