fix(dn): Move Tyler DN to correct file (#493)

Author: dareminion

Tylerlee102:patch-2

@@ -0,0 +1,30 @@
+# Design Notebook — Tyler
+
+## Week 1: 01/20/26 – 01/25/26
+* **Meeting 1**: Met with the team to discuss the initial project scope and repository setup.
+* **Goals**: Familiarize myself with the RiSC-16 architecture and established project workflows.
+
+---
+
+## Week 2: 01/26/26 – 02/01/26
+* **Meeting 2**: Met with Danish on Thursday at 1:00 PM.
+* **Work Completed**:
+    * Implemented initial logic for `pc.v` and `instruction_memory.v` based on the lecture slides.
+    * **Dependencies**: `instruction_memory.v` appears to require an external file or module that is currently missing from the local environment.
+
+## Week 3: 02/02/26 – 02/08/26
+* **Meeting 2**: Met with Danish on Thursday at 1:00 PM and talked to Noahm and he explained to use the different parts of the 16 bit processor and the difference between the memmory and why we are coding it this certain way.
+* **Work Completed**:
+    * Implemented initial logic for `data_memory.v` and `alu.v` based on the lecture slides.
+
+## Week 4: 02/09/26 – 02/15/26
+* **Meeting 3**: Focused on completing the core datapath and control modules for the RiSC-16.
+* **Work Completed**:
+    * Implemented the Register File (`register_file.v`) with eight 16-bit registers.
+    * Created the Control Module (`control.v`) to tie each section of the processor together using only the 3-bit opcode.
+
+
+## Week 5: 02/16/26 – 02/22/26
+* **Meeting 4**: Discussed the importance of verification as a vital step in processor design and entry-level hardware roles.
+* **Work Completed**:
+    * Developed the ALU Testbench (`alu_tb.v`) with a timescale of 1ns / 1ps for functional simulation.