Docs(dn): Tony Korycki 4/5/2026 (#525)

* docs(dn): Tony_02_01_2026

* docs(dn) Tony Korycki 2/15/26

* docs(dn) Tony, 3/9/26

* fix dates in notebook

* docs(dn) Tony Korycki 3/27/26

* docs(dn) Tony Korycki 4/5/2026

Author: tonykorycki

src/design_notebooks/2026spring/ajk8795.md

@@ -1,8 +1,46 @@
-## Week 1: 01/25-02/01/2026
-
-- Read the syllabus and sections 1-4 on the VIP's website
-- Installed all required extensions and set up my VM through VirtualBox
-- Found a partner (Gloria) for the RiSC-16 onboarding project and we scheduled our first meeting for Friday 
-- Read the slides fo the onboarding project and the ones from the first in-person meeting
-
-I already had WSL set up and was familiar with using Git so I didnt run into many issues getting started. The website was very clear and easy to follow. 
+## Week 1: 01/25-02/01/2026
+
+- Read the syllabus and sections 1-4 on the VIP's website
+- Installed all required extensions and set up my VM through VirtualBox
+- Found a partner (Gloria) for the RiSC-16 onboarding project and we scheduled our first meeting for Friday 
+- Read the slides fo the onboarding project and the ones from the first in-person meeting
+
+I already had WSL set up and was familiar with using Git so I didnt run into many issues getting started. The website was very clear and easy to follow. 
+
+## Week 2: 02/01-02/08/2026
+
+- Went thorough the first week of onboarding - created the PC and Memeory moedules with teammate Gloria. We also mistakenly did the first onboarding lab with CMake. 
+- We added our work to a (github repo)[https://github.com/tonykorycki/risc16-onboarding] and I walked gloria thorugh using git and github to collaborate.
+- Setting up the verilog modules went smoothly cause we already both have experience with verilog. We also set up some testbenches for the modules and tried them out in Icarus Verilog.
+
+
+## Week 3: 02/08-02/15/2026
+
+- We continued working on the onboarding project and added the ALU module and the data memory module. Did not add testbenches for those but again went smoothly.
+- We are still a little confusde about what kind of notes we need to include.
+
+## Week 4: 02/15-02/22/2026
+- We added the register file module and the control unit module. We had some scheduiling issues so we didnt meet and instead worked on the modules separately.
+- Compiled with iverilog and they seem to work. will see once we add testbwnches
+- 
+## Week 5: 02/22-03/01/2026
+- We added the testbenches for the ALU, and it worked fine
+- not much else
+
+## Week 6: 03/02-03/08/2026
+- added the top level module for the processor and added a testbench for it. We had some issues with the testbench cause the naming was different bwtween the modules in the tb and in out file
+- and we forgot to connect some signals to the reg file
+- and also som eof the instructions in program.mem were wrong so we had to fix those as well
+- after fixing all that our processor worked perfectly! (github repo)[https://github.com/tonykorycki/risc16-onboarding]
+
+# Weeks 7-9: 03/08-03/29/2026
+- Didn't work during spring break, but completed labs 1 and 2 this week for onboarding and all the work in [this repo](https://github.com/tonykorycki/proc-des-onboarding-labs)
+- Labs werent too hard but I ran into some issues with my tools and spent some time fixing imports venvs, settings etc
+- for lab 2, i couldnt get the testbenches working and used codex to resolve some issues. it worked (and all tests passed) after:
+  - casting uniform_int_distribution<int> to uint8_t in exercise3.cpp tet
+  - adding a sim_time.cpp to resolve verilator expecting a timestamp shim in the testbench linkage
+- I chose to clone the lab repo and unlink it rather than forking so i could have all my labs in one repo and make linking in the notebook easier.
+
+# Week 8: 03/29-04/05/2026
+- Completed lab 3 without much trouble, got started on lab 4.
+- Havent gotten a group or a porject idea for th MPW yet.