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Specifies the architecture for code generation on x64. These switches apply to the x64 targeting version of the compiler. For more information on **`/arch`** for other target architectures, see [`/arch` (x86)](arch-x86.md), [`/arch` (ARM64)](arch-arm64.md), and [`/arch` (ARM)](arch-arm.md).
Enables Intel Advanced Vector Extensions 10 version 1.
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**`/arch:AVX10.2`**\
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Enables Intel Advanced Vector Extensions 10 version 2.
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## Remarks
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The **`/arch`** option enables the use of certain instruction set extensions, particularly for vector calculation, available in processors from Intel and AMD. In general, more recently introduced processors may support extensions beyond the ones supported by older processors, although you should consult the documentation for a particular processor or test for instruction set extension support using [`__cpuid`](../../intrinsics/cpuid-cpuidex.md) before executing code using an instruction set extension. You can also use the [`__check_isa_support`](../../intrinsics/check-isa-arch-support.md) intrinsic to check for more frequently used CPU features.
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-**`AVX-512`** introduced another instruction encoding form that allows 512-bit vectors, masking, embedded rounding/broadcast, and new instructions. The default vector length for **`AVX-512`** is 512 bits and can be changed to 256 bits using the [`/vlen`](vlen.md) flag.
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-**`AVX10.1`** adds more instructions on top of **`AVX-512`**. The default vector length for **`AVX10.1`** is 256 bits and can be changed to 512 bits using the [`/vlen`](vlen.md) flag.
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-**`AVX10.1`** adds more instructions on top of **`AVX-512`**. The default vector length for **`AVX10.1`** is 256 bits and can be changed to 512 bits using the [`/vlen`](vlen.md) flag. This option was introduced in Visual Studio 2022 17.13.
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-**`AVX10.2`** expands the instruction set introduced in `AVX10.1`. The default vector length for **`AVX10.2`** is 256 bits and can be increased to 512 bits using the [`/vlen`](vlen.md) flag.
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`AVX10.2` adds instructions that are enhancements of legacy instructions and media acceleration instructions. For more information about the new instructions, see section 3.1.4 in the [Intel Advanced Vector Extensions 10.2 Architecture Specification](https://www.intel.com/content/www/us/en/content-details/856721/intel-advanced-vector-extensions-10-2-intel-avx10-2-architecture-specification.html). The AI related instructions in that document are supported via MSVC intrinsics instead of being directly emitted because MSVC doesn't support their data types. This compiler option was introduced in Visual Studio 2026.
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Each **`/arch`** option may also enable the use of other non-vector instructions that are associated with that option. An example is the use of certain BMI instructions when **`/arch:AVX2`** is specified.
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Each **`/arch`** option may also enable the use of other nonvector instructions that are associated with that option. An example is the use of certain BMI instructions when **`/arch:AVX2`** is specified.
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The `__AVX__` preprocessor symbol is defined when the **`/arch:AVX`**, **`/arch:AVX2`**, **`/arch:AVX512`**, or **`/arch:AVX10.1`** compiler option is specified.
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The `__AVX2__` preprocessor symbol is defined when the **`/arch:AVX2`**, **`/arch:AVX512`**, or **`/arch:AVX10.1`** compiler option is specified.
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The `__AVX512F__`, `__AVX512CD__`, `__AVX512BW__`, `__AVX512DQ__`, and `__AVX512VL__` preprocessor symbols are defined when the **`/arch:AVX512`**, or **`/arch:AVX10.1`** compiler option is specified.
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The `__AVX10_VER__` preprocessor symbol is defined when the **`/arch:AVX10.1`** compiler option is specified. It indicates the AVX10 version the compiler is targeting. For more information, see [Predefined macros](../../preprocessor/predefined-macros.md).
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The `__AVX__` preprocessor symbol is defined when the **`/arch:AVX`**, **`/arch:AVX2`**, **`/arch:AVX512`**, **`/arch:AVX10.1`**, or **`/arch:AVX10.2`** compiler option is specified.
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The `__AVX2__` preprocessor symbol is defined when the **`/arch:AVX2`**, **`/arch:AVX512`**, **`/arch:AVX10.1`**, or **`/arch:AVX10.2`** compiler option is specified.
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The `__AVX512F__`, `__AVX512CD__`, `__AVX512BW__`, `__AVX512DQ__`, and `__AVX512VL__` preprocessor symbols are defined when the **`/arch:AVX512`**, **`/arch:AVX10.1`**, or **`/arch:AVX10.2`** compiler option is specified.
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The `__AVX10_VER__` preprocessor symbol is defined when the **`/arch:AVX10.1`**or **`/arch:AVX10.2`**compiler option is specified. It indicates the AVX10 version the compiler is targeting. For more information, see [Predefined macros](../../preprocessor/predefined-macros.md).
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The **`/arch:AVX2`** option was introduced in Visual Studio 2013 Update 2, version 12.0.34567.1.
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Limited support for **`/arch:AVX512`** was added in Visual Studio 2017, and expanded in Visual Studio 2019.
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Support for **`/arch:AVX10.1`** was added in Visual Studio 2022.
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Support for **`/arch:AVX10.1`** was added in Visual Studio 2022. Support for **`/arch:AVX10.2`** was added in Visual Studio 2026.
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### To set the `/arch` compiler option in Visual Studio
Specifies the architecture for code generation on x86. These switches apply to the x86 (32-bit) targeting version of the compiler. For more information on **`/arch`** for other target architectures, see [`/arch` (ARM64)](arch-arm64.md), [`/arch` (x64)](arch-x64.md), and [`/arch` (ARM)](arch-arm.md).
Enables Intel Advanced Vector Extensions 10 version 1.
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**`/arch:AVX10.2`**\
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Enables Intel Advanced Vector Extensions 10 version 2.
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## Remarks
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The **`/arch`** option enables or disables the use of certain instruction set extensions, particularly for vector calculation, available in processors from Intel and AMD. In general, more recently introduced processors may support extensions beyond the ones supported by older processors. You should consult the documentation for a particular processor or test for instruction set extension support using [`__cpuid`](../../intrinsics/cpuid-cpuidex.md) before executing code using an instruction set extension. You can also use the [`__check_isa_support`](../../intrinsics/check-isa-arch-support.md) intrinsic to check for more frequently used CPU features.
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-**`AVX512`** introduced another instruction encoding form that allows 512-bit vectors, masking, embedded rounding/broadcast, and new instructions. The default vector length for **`AVX512`** is 512 bits and can be changed to 256 bits using the [`/vlen`](vlen.md) flag.
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-**`AVX10.1`** adds more instructions on top of **`AVX-512`**. The default vector length for **`AVX10.1`** is 256 bits and can be changed to 512 bits using the [`/vlen`](vlen.md) flag.
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-**`AVX10.1`** adds more instructions on top of **`AVX-512`**. The default vector length for **`AVX10.1`** is 256 bits and can be changed to 512 bits using the [`/vlen`](vlen.md) flag. This option was introduced in Visual Studio 2022 17.13.
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-**`AVX10.2`** expands the instruction set introduced in `AVX10.1`. The default vector length for **`AVX10.2`** is 256 bits and can be increased to 512 bits using the [`/vlen`](vlen.md) flag.
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`AVX10.2` adds instructions that are enhancements of legacy instructions and media acceleration instructions. For more information about the new instructions, see section 3.1.4 in the [Intel Advanced Vector Extensions 10.2 Architecture Specification](https://www.intel.com/content/www/us/en/content-details/856721/intel-advanced-vector-extensions-10-2-intel-avx10-2-architecture-specification.html) The AI related instructions in that document are supported via MSVC intrinsics instead of being directly emitted because MSVC doesn't support their data types. This compiler option was introduced in Visual Studio 2026.
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The optimizer chooses when and how to use vector instructions depending on which **`/arch`** is specified. Scalar floating-point computations are usually performed with SSE or AVX instructions when available. Some calling conventions specify passing floating-point arguments on the x87 stack, and as a result, your code may use a mixture of both x87 and SSE/AVX instructions for floating-point computations. Integer vector instructions can also be used for some 64-bit integer operations when available.
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In addition to the vector and floating-point scalar instructions, each **`/arch`** option may also enable the use of other non-vector instructions that are associated with that option. An example is the CMOVcc instruction family that first appeared on the Intel Pentium Pro processors. Because SSE instructions were introduced with the subsequent Intel Pentium III processor, CMOVcc instructions may be generated except when **`/arch:IA32`** is specified.
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In addition to the vector and floating-point scalar instructions, each **`/arch`** option may also enable the use of other nonvector instructions that are associated with that option. An example is the CMOVcc instruction family that first appeared on the Intel Pentium Pro processors. Because SSE instructions were introduced with the subsequent Intel Pentium III processor, CMOVcc instructions may be generated except when **`/arch:IA32`** is specified.
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Floating-point operations are normally rounded to double-precision (64-bit) in x87 code, but you can use `_controlfp` to modify the FP control word, including setting the precision control to extended precision (80-bit) or single-precision (32-bit). For more information, see [`_control87`, `_controlfp`, `__control87_2`](../../c-runtime-library/reference/control87-controlfp-control87-2.md). SSE and AVX have separate single-precision and double-precision instructions for each operation, so there's no equivalent for SSE/AVX code. It can change how results are rounded when the result of a floating-point operation is used directly in further calculation instead of assigning it to a user variable. Consider the following operations:
Specifies the vector length for code generation on x86 and x64. For more information about **`/arch`** for x86 and x64, see [`/arch` (x86)](arch-x86.md) and [`/arch` (x64)](arch-x64.md).
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## Syntax
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> **`/vlen=`**\[**`256`**|**`512`**]
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## Arguments
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**`/vlen=256`**\
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Specify a vector length of 256 bits for auto-vectorization and other optimizations.
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Specify a vector length of 256 bits for autovectorization and other optimizations.
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**`/vlen=512`**\
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Specify a vector length of 512 bits for auto-vectorization and other optimizations.
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Specify a vector length of 512 bits for autovectorization and other optimizations.
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**`/vlen`**\
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Specify the default vector length for the selected **`/arch`** setting.
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## Remarks
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If a specific **`/vlen`** value isn't specified, the default vector length depends on the **`/arch`** flag setting. The **`/vlen`** flag can override the default vector length specified by **`/arch:AVX512`** or **`/arch:AVX10.1`** flag. For example:
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This compiler option was introduced in Visual Studio 2022 17.13.
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If a specific **`/vlen`** value isn't specified, the default vector length depends on the **`/arch`** compiler option setting. The **`/vlen`** compiler option can override the default vector length specified by **`/arch:AVX512`**, **`/arch:AVX10.1`**, or **`/arch:AVX10.2`** compiler option. For example:
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-**`/arch:AVX512 /vlen=256`** overrides the default vector length of 512 bits specified by **`/arch:AVX512`** to be 256 bits.
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-**`/arch:AVX10.1 /vlen=512`** overrides the default vector length of 256 bits specified by **`/arch:AVX10.1`** to be 512 bits.
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When the specified **`/vlen`** value is incompatible with specified **`/arch`**flag, a warning is generated and default vector length for the **`/arch`** setting is used. For example:
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When the specified **`/vlen`** value is incompatible with specified **`/arch`**compiler option, a warning is generated and default vector length for the **`/arch`** setting is used. For example:
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-**`/arch:AVX2 /vlen=512`** generates a warning because AVX2 doesn't support 512-bit vectors. Vector length of 256 bits is used in this case.
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-**`/arch:AVX2 /vlen=512`** generates a warning because AVX2 doesn't support 512-bit vectors. A 256-bit vector length is used in this case.
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### To set the `/vlen=256` or `/vlen=512` compiler option in Visual Studio
![learn-build-service-prod[bot]](https://avatars.githubusercontent.com/in/237442?v=4&size=40){kind=avatar}
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