implement xor, or, and and

Author: outercloudstudio

documentation/Modules/Hart.md

@@ -26,11 +26,11 @@ Currently only the `LW` instruction uses stage 2, since in stage 1 `LW` requests
 - [x] SLL
 - [x] SLT
 - [x] SLTU
-- [ ] XOR
+- [x] XOR
 - [ ] SRL
 - [ ] SRA
-- [ ] OR
-- [ ] AND
+- [x] OR
+- [x] AND
 - [ ] LB
 - [ ] LH
 - [x] LW

src/main/scala/RISCV/Main.scala

@@ -362,6 +362,51 @@ class Main() extends Module {
 
                     printf("[SLTU] Rs1: %d Rs2: %d Rd: %d\n", decoder.io.rs1, decoder.io.rs2, decoder.io.rd);
                 }
+
+                // XOR
+                is("b100_0110011".U) { 
+                    registers.io.read_address_a := decoder.io.rs1;
+                    registers.io.read_address_b := decoder.io.rs2;
+
+                    registers.io.write_address := decoder.io.rd;
+                    registers.io.write_enable := true.B;
+                    registers.io.in := registers.io.out_a ^ registers.io.out_b;
+
+                    program_pointer := program_pointer + 1.U;
+                    stage := 0.U;
+
+                    printf("[XOR] Rs1: %d Rs2: %d Rd: %d\n", decoder.io.rs1, decoder.io.rs2, decoder.io.rd);
+                }
+
+                // OR
+                is("b110_0110011".U) { 
+                    registers.io.read_address_a := decoder.io.rs1;
+                    registers.io.read_address_b := decoder.io.rs2;
+
+                    registers.io.write_address := decoder.io.rd;
+                    registers.io.write_enable := true.B;
+                    registers.io.in := registers.io.out_a | registers.io.out_b;
+
+                    program_pointer := program_pointer + 1.U;
+                    stage := 0.U;
+
+                    printf("[OR] Rs1: %d Rs2: %d Rd: %d\n", decoder.io.rs1, decoder.io.rs2, decoder.io.rd);
+                }
+
+                // AND
+                is("b111_0110011".U) { 
+                    registers.io.read_address_a := decoder.io.rs1;
+                    registers.io.read_address_b := decoder.io.rs2;
+
+                    registers.io.write_address := decoder.io.rd;
+                    registers.io.write_enable := true.B;
+                    registers.io.in := registers.io.out_a & registers.io.out_b;
+
+                    program_pointer := program_pointer + 1.U;
+                    stage := 0.U;
+
+                    printf("[AND] Rs1: %d Rs2: %d Rd: %d\n", decoder.io.rs1, decoder.io.rs2, decoder.io.rd);
+                }
             }
         }