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WIP: reduce to 32-bit again... 64-bit registers aren't "atomic"
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1 file changed

+11
-8
lines changed
  • software/glasgow/applet/interface/freq_counter

1 file changed

+11
-8
lines changed

software/glasgow/applet/interface/freq_counter/__init__.py

Lines changed: 11 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -47,7 +47,7 @@ def elaborate(self, platform):
4747
rst=trigger,
4848
clk=self.pads.i_t.i,
4949
clk_en=self.running,
50-
width=64,
50+
width=32,
5151
)
5252
m.d.comb += self.edge_count.eq(m.submodules.ripple.count)
5353

@@ -63,7 +63,7 @@ async def configure(self, duration=2.0):
6363
ctr = int(self.applet.sys_clk_freq * duration)
6464

6565
# this is broken (see comment below)
66-
#await self.device.write_register(self.applet.__reg_clk_count, ctr, width=8)
66+
#await self.device.write_register(self.applet.__reg_clk_count, ctr, width=4)
6767

6868
await self.applet.set_clk_count(ctr)
6969

@@ -115,8 +115,8 @@ def add_build_arguments(cls, parser, access):
115115
def build(self, target, args):
116116
self.mux_interface = iface = target.multiplexer.claim_interface(self, args)
117117

118-
reg_clk_count, self.__reg_clk_count = target.registers.add_rw(64)
119-
reg_edge_count, self.__reg_edge_count = target.registers.add_ro(64)
118+
reg_clk_count, self.__reg_clk_count = target.registers.add_rw(32)
119+
reg_edge_count, self.__reg_edge_count = target.registers.add_ro(32)
120120
reg_running, self.__reg_running = target.registers.add_ro(1)
121121

122122
subtarget = iface.add_subtarget(FrequencyCounterSubtarget(
@@ -174,16 +174,19 @@ async def interact(self, device, args, freq_ctr):
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# File "/home/attie/proj_local/glasgow/glasgow/software/glasgow/applet/interface/freq_counter/__init__.py", line 85, in measure
175175
# await self.configure(duration)
176176
# File "/home/attie/proj_local/glasgow/glasgow/software/glasgow/applet/interface/freq_counter/__init__.py", line 60, in configure
177-
# await self.device.write_register(self.applet.__reg_clk_count, ctr, width=8)
177+
# await self.device.write_register(self.applet.__reg_clk_count, ctr, width=4)
178178
# AttributeError: 'FrequencyCounterApplet' object has no attribute '_FrequencyCounterInterface__reg_clk_count'
179179

180180
async def get_clk_count(self):
181-
return await self.device.read_register(self.__reg_clk_count, width=8)
181+
return await self.device.read_register(self.__reg_clk_count, width=4)
182182
async def set_clk_count(self, value):
183-
await self.device.write_register(self.__reg_clk_count, value, width=8)
183+
await self.device.write_register(self.__reg_clk_count, value, width=4)
184+
185+
async def get_ctr(self):
186+
return await self.device.read_register(self.__reg_ctr, width=4)
184187

185188
async def get_edge_count(self):
186-
return await self.device.read_register(self.__reg_edge_count, width=8)
189+
return await self.device.read_register(self.__reg_edge_count, width=4)
187190

188191
async def get_running(self):
189192
return bool(await self.device.read_register(self.__reg_running, width=1))

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