CPU/all8equal.circ at main · FISHARMNIC/CPU · GitHub

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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<project source="3.8.0" version="1.0">
  This file is intended to be loaded by Logisim-evolution v3.8.0(https://github.com/logisim-evolution/).

  <lib desc="#Wiring" name="0">
    <tool name="Pin">
      <a name="appearance" val="classic"/>
    </tool>
  </lib>
  <lib desc="#Gates" name="1"/>
  <lib desc="#Plexers" name="2"/>
  <lib desc="#Arithmetic" name="3"/>
  <lib desc="#Memory" name="4"/>
  <lib desc="#I/O" name="5"/>
  <lib desc="#TTL" name="6"/>
  <lib desc="#TCL" name="7"/>
  <lib desc="#Base" name="8"/>
  <lib desc="#BFH-Praktika" name="9"/>
  <lib desc="#Input/Output-Extra" name="10"/>
  <lib desc="#Soc" name="11"/>
  <main name="main"/>
  <options>
    <a name="gateUndefined" val="ignore"/>
    <a name="simlimit" val="1000"/>
    <a name="simrand" val="0"/>
  </options>
  <mappings>
    <tool lib="8" map="Button2" name="Poke Tool"/>
    <tool lib="8" map="Button3" name="Menu Tool"/>
    <tool lib="8" map="Ctrl Button1" name="Menu Tool"/>
  </mappings>
  <toolbar>
    <tool lib="8" name="Poke Tool"/>
    <tool lib="8" name="Edit Tool"/>
    <tool lib="8" name="Wiring Tool"/>
    <tool lib="8" name="Text Tool"/>
    <sep/>
    <tool lib="0" name="Pin"/>
    <tool lib="0" name="Pin">
      <a name="facing" val="west"/>
      <a name="output" val="true"/>
    </tool>
    <sep/>
    <tool lib="1" name="NOT Gate"/>
    <tool lib="1" name="AND Gate"/>
    <tool lib="1" name="OR Gate"/>
    <tool lib="1" name="XOR Gate"/>
    <tool lib="1" name="NAND Gate"/>
    <tool lib="1" name="NOR Gate"/>
    <sep/>
    <tool lib="4" name="D Flip-Flop"/>
    <tool lib="4" name="Register"/>
  </toolbar>
  <circuit name="main">
    <a name="circuit" val="main"/>
    <a name="circuitnamedboxfixedsize" val="true"/>
    <a name="simulationFrequency" val="1.0"/>
    <comp lib="0" loc="(1110,2090)" name="Pin">
      <a name="appearance" val="classic"/>
      <a name="width" val="8"/>
    </comp>
    <comp lib="0" loc="(1110,2110)" name="Pin">
      <a name="appearance" val="classic"/>
      <a name="width" val="8"/>
    </comp>
    <comp lib="0" loc="(1160,2100)" name="Splitter">
      <a name="fanout" val="8"/>
      <a name="incoming" val="8"/>
    </comp>
    <comp lib="0" loc="(1250,2060)" name="Pin">
      <a name="appearance" val="classic"/>
      <a name="facing" val="west"/>
      <a name="output" val="true"/>
    </comp>
    <comp lib="1" loc="(1160,2100)" name="XNOR Gate">
      <a name="size" val="30"/>
      <a name="width" val="8"/>
    </comp>
    <comp lib="1" loc="(1250,2060)" name="AND Gate">
      <a name="inputs" val="8"/>
      <a name="size" val="30"/>
    </comp>
    <wire from="(1180,2020)" to="(1220,2020)"/>
    <wire from="(1180,2030)" to="(1220,2030)"/>
    <wire from="(1180,2040)" to="(1220,2040)"/>
    <wire from="(1180,2050)" to="(1220,2050)"/>
    <wire from="(1180,2060)" to="(1210,2060)"/>
    <wire from="(1180,2070)" to="(1200,2070)"/>
    <wire from="(1180,2080)" to="(1190,2080)"/>
    <wire from="(1180,2090)" to="(1180,2100)"/>
    <wire from="(1180,2100)" to="(1220,2100)"/>
    <wire from="(1190,2080)" to="(1190,2090)"/>
    <wire from="(1190,2090)" to="(1220,2090)"/>
    <wire from="(1200,2070)" to="(1200,2080)"/>
    <wire from="(1200,2080)" to="(1220,2080)"/>
    <wire from="(1210,2060)" to="(1210,2070)"/>
    <wire from="(1210,2070)" to="(1220,2070)"/>
  </circuit>
</project>