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jakubcabaljakubcabal
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Merge branch 'spinler-fix-vhdl_repeated_declaration' into 'devel'
Spinler fix vhdl repeated declaration See merge request ndk/ndk-fpga!344
2 parents ad7c7a4 + 5f952da commit ef2cee4

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3 files changed

+41
-43
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3 files changed

+41
-43
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‎comp/base/fifo/fifo_bram_xilinx/fifo_bram_xilinx.vhd‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -26,16 +26,16 @@ begin
2626

2727
v6_v7_gen : if DEVICE = "VIRTEX6" or DEVICE = "7SERIES" generate
2828

29-
constant I : integer := tsel(
29+
constant ITEMS_CEIL : integer := tsel(
3030
ITEMS <= 512, 512, tsel(
3131
ITEMS <= 1024, 1024, tsel(
3232
ITEMS <= 2048, 2048, tsel(
3333
ITEMS <= 4096, 4096, 8192
3434
))));
35-
constant DW36D : integer := 32768 / I;
35+
constant DW36D : integer := 32768 / ITEMS_CEIL;
3636
constant DW36P : integer := DW36D / 8;
3737
constant DW36 : integer := DW36D + DW36P;
38-
constant DW18D : integer := tsel(I = 8192, 0, 16384 / I);
38+
constant DW18D : integer := tsel(ITEMS_CEIL = 8192, 0, 16384 / ITEMS_CEIL);
3939
constant DW18P : integer := DW18D / 8;
4040
constant DW18 : integer := DW18D + DW18P;
4141
constant ROWS : integer := ((DATA_WIDTH-1) / DW36) + 1;
@@ -247,21 +247,21 @@ begin
247247

248248
us_gen : if DEVICE = "ULTRASCALE" generate
249249

250-
constant I : integer := tsel(
250+
constant ITEMS_CEIL : integer := tsel(
251251
ITEMS <= 512, 512, tsel(
252252
ITEMS <= 1024, 1024, tsel(
253253
ITEMS <= 2048, 2048, tsel(
254254
ITEMS <= 4096, 4096, 8192
255255
))));
256-
constant DW36D : integer := 32768 / I;
256+
constant DW36D : integer := 32768 / ITEMS_CEIL;
257257
constant DW36P : integer := DW36D / 8;
258258
constant DW36 : integer := DW36D + DW36P;
259-
constant DW18D : integer := tsel(I = 8192, 0, 16384 / I);
259+
constant DW18D : integer := tsel(ITEMS_CEIL = 8192, 0, 16384 / ITEMS_CEIL);
260260
constant DW18P : integer := DW18D / 8;
261261
constant DW18 : integer := DW18D + DW18P;
262262
constant ROWS : integer := ((DATA_WIDTH-1) / DW36) + 1;
263263
constant LAST18 : boolean := (DATA_WIDTH - ((ROWS-1)*DW36)) <= DW18;
264-
constant PROG_FULL_THRESH : integer := I - ALMOST_FULL_OFFSET;
264+
constant PROG_FULL_THRESH : integer := ITEMS_CEIL - ALMOST_FULL_OFFSET;
265265

266266
signal di_rows : std_logic_vector(DW36*ROWS-1 downto 0) := (others => '0');
267267
signal do_rows : std_logic_vector(DW36*ROWS-1 downto 0) := (others => '0');

‎comp/base/logic/count/count_dsp.vhd‎

Lines changed: 22 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -256,25 +256,25 @@ begin
256256
signal array_pom_out : array_pom_out_t;
257257
begin
258258
--! generate output registers
259-
gen_reg_out: for i in 0 to ((DATA_WIDTH/48) + (1 mod ((DATA_WIDTH mod 48) +1)) - 2) generate
259+
gen_reg_out: for y in 0 to ((DATA_WIDTH/48) + (1 mod ((DATA_WIDTH mod 48) +1)) - 2) generate
260260
process (CLK)
261261
begin
262262
if ((CLK'event) and (CLK = '1')) then
263-
-- if (enable_p(2+I) = '1') then
264-
array_pom_out(I + 1) <= array_pom_out(I);
263+
-- if (enable_p(2+y) = '1') then
264+
array_pom_out(y + 1) <= array_pom_out(y);
265265
-- end if;
266266
end if;
267267
end process;
268268
end generate;
269269

270270
--! generate registers for DSP pattern output
271271
gen_rst_logic: if (AUTO_RESET = 1) generate
272-
gen_reg_out: for i in 0 to ((DATA_WIDTH/48) + (1 mod ((DATA_WIDTH mod 48) +1)) - 2) generate
272+
gen_reg_out: for y in 0 to ((DATA_WIDTH/48) + (1 mod ((DATA_WIDTH mod 48) +1)) - 2) generate
273273
process (CLK)
274274
begin
275275
if ((CLK'event) and (CLK = '1')) then
276-
-- if (enable_p(2+I) = '1') then
277-
pattern_pom(I + 1) <= pattern_pom(I);
276+
-- if (enable_p(2+y) = '1') then
277+
pattern_pom(y + 1) <= pattern_pom(y);
278278
-- end if;
279279
end if;
280280
end process;
@@ -321,8 +321,8 @@ begin
321321
process (CLK)
322322
begin
323323
if ((CLK'event) and (CLK = '1')) then
324-
-- if (enable_p(I+2+Y) = '1') then
325-
array_pom_out(Y + 1) <= array_pom_out(Y);
324+
-- if (enable_p(I+2+y) = '1') then
325+
array_pom_out(y + 1) <= array_pom_out(y);
326326
-- end if;
327327
end if;
328328
end process;
@@ -333,8 +333,8 @@ begin
333333
process (CLK)
334334
begin
335335
if ((CLK'event) and (CLK = '1')) then
336-
-- if (enable_p(I+2+Y) = '1') then
337-
pattern_pom(Y + 1) <= pattern_pom(Y);
336+
-- if (enable_p(I+2+y) = '1') then
337+
pattern_pom(y + 1) <= pattern_pom(y);
338338
-- end if;
339339
end if;
340340
end process;
@@ -346,8 +346,8 @@ begin
346346
process (CLK)
347347
begin
348348
if ((CLK'event) and (CLK = '1')) then
349-
-- if (enable_p(1+Y) = '1') then
350-
array_pom_in_A(Y + 1) <= array_pom_in_A(Y);
349+
-- if (enable_p(1+y) = '1') then
350+
array_pom_in_A(y + 1) <= array_pom_in_A(y);
351351
-- end if;
352352
end if;
353353
end process;
@@ -359,8 +359,8 @@ begin
359359
process (CLK)
360360
begin
361361
if ((CLK'event) and (CLK = '1')) then
362-
-- if (enable_p(1+Y) = '1') then
363-
array_pom_in_MAX(Y + 1) <= array_pom_in_MAX(Y);
362+
-- if (enable_p(1+y) = '1') then
363+
array_pom_in_MAX(y + 1) <= array_pom_in_MAX(y);
364364
-- end if;
365365
end if;
366366
end process;
@@ -407,8 +407,8 @@ begin
407407
process (CLK)
408408
begin
409409
if ((CLK'event) and (CLK = '1')) then
410-
-- if (enable_p(1+Y) = '1') then
411-
array_pom_in_A(Y + 1) <= array_pom_in_A(Y);
410+
-- if (enable_p(1+y) = '1') then
411+
array_pom_in_A(y + 1) <= array_pom_in_A(y);
412412
-- end if;
413413
end if;
414414
end process;
@@ -419,8 +419,8 @@ begin
419419
process (CLK)
420420
begin
421421
if ((CLK'event) and (CLK = '1')) then
422-
-- if (enable_p(1+Y) = '1') then
423-
array_pom_in_MAX(Y + 1) <= array_pom_in_MAX(Y);
422+
-- if (enable_p(1+y) = '1') then
423+
array_pom_in_MAX(y + 1) <= array_pom_in_MAX(y);
424424
-- end if;
425425
end if;
426426
end process;
@@ -465,8 +465,8 @@ begin
465465
process (CLK)
466466
begin
467467
if ((CLK'event) and (CLK = '1')) then
468-
-- if (enable_p(1+Y) = '1') then
469-
array_pom_in_A(Y + 1) <= array_pom_in_A(Y);
468+
-- if (enable_p(1+y) = '1') then
469+
array_pom_in_A(y + 1) <= array_pom_in_A(y);
470470
-- end if;
471471
end if;
472472
end process;
@@ -477,8 +477,8 @@ begin
477477
process (CLK)
478478
begin
479479
if ((CLK'event) and (CLK = '1')) then
480-
-- if (enable_p(1+Y) = '1') then
481-
array_pom_in_MAX(Y + 1) <= array_pom_in_MAX(Y);
480+
-- if (enable_p(1+y) = '1') then
481+
array_pom_in_MAX(y + 1) <= array_pom_in_MAX(y);
482482
-- end if;
483483
end if;
484484
end process;

‎comp/pcie/ptc/comp/pcie2dma_hdr_transform/ptc_pcie2dma_hdr_transform_full.vhd‎

Lines changed: 12 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -114,20 +114,18 @@ begin
114114
);
115115
end generate;
116116

117-
rx_sel_gen : for i in 0 to MVB_ITEMS-1 generate
118-
tag_rel_reg_pr : process (CLK)
119-
begin
120-
if (rising_edge(CLK)) then
121-
for i in 0 to MVB_ITEMS-1 loop
122-
TAG(PCIE_TAG_WIDTH*(i+1)-1 downto PCIE_TAG_WIDTH*i) <= rx_mvb_pcie_tag(i)(PCIE_TAG_WIDTH-1 downto 0);
123-
TAG_COMPL_LOW_ADDR(PCIE_LOW_ADDR_WIDTH*(i+1)-1 downto PCIE_LOW_ADDR_WIDTH*i) <= rx_mvb_low_addr(i)(PCIE_LOW_ADDR_WIDTH-1 downto 0);
124-
TAG_COMPL_LEN(DMA_LEN_WIDTH*(i+1)-1 downto DMA_LEN_WIDTH*i) <= rx_mvb_len(i);
125-
TAG_RELEASE(i) <= rx_mvb_complete(i) and rx_mvb_vld_reg0(i);
126-
TAG_VLD(i) <= rx_mvb_vld_reg0(i);
127-
end loop;
128-
end if;
129-
end process;
130-
end generate;
117+
tag_rel_reg_pr : process (CLK)
118+
begin
119+
if (rising_edge(CLK)) then
120+
for i in 0 to MVB_ITEMS-1 loop
121+
TAG(PCIE_TAG_WIDTH*(i+1)-1 downto PCIE_TAG_WIDTH*i) <= rx_mvb_pcie_tag(i)(PCIE_TAG_WIDTH-1 downto 0);
122+
TAG_COMPL_LOW_ADDR(PCIE_LOW_ADDR_WIDTH*(i+1)-1 downto PCIE_LOW_ADDR_WIDTH*i) <= rx_mvb_low_addr(i)(PCIE_LOW_ADDR_WIDTH-1 downto 0);
123+
TAG_COMPL_LEN(DMA_LEN_WIDTH*(i+1)-1 downto DMA_LEN_WIDTH*i) <= rx_mvb_len(i);
124+
TAG_RELEASE(i) <= rx_mvb_complete(i) and rx_mvb_vld_reg0(i);
125+
TAG_VLD(i) <= rx_mvb_vld_reg0(i);
126+
end loop;
127+
end if;
128+
end process;
131129

132130
-- -------------------------------------------------------------------------
133131

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