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Commit 041be6f

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author
Stepan Friedl
committed
Merge branch 'friedl-fix-ftile_drp' into 'devel'
Fix F-Tile XCVR initialization, also fix unreliable PMA loopback See merge request ndk/ndk-fpga!358
2 parents e1abaac + d462aec commit 041be6f

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10 files changed

+78
-75
lines changed

10 files changed

+78
-75
lines changed

‎core/comp/eth/network_mod/comp/network_mod_core/comps/ftile/ftile_1x400g8.vhd‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -526,12 +526,12 @@ begin
526526
STATE => open -- debug purposes only. Can be left open in the future
527527
);
528528

529-
end generate;
529+
mi_ardy_phy(IA_INDEX) <= not reconfig_waitrequest(IA_INDEX) and not init_busy;
530530

531-
mi_ardy_conversion_g: for i in PMA_LANES downto 0 generate
532-
mi_ardy_phy(i) <= not reconfig_waitrequest(i);
533531
end generate;
534532

533+
mi_ardy_phy(0) <= not reconfig_waitrequest(0);
534+
535535
CLK_ETH_OUT <= ftile_clk_out;
536536

537537
-- =========================================================================

‎core/comp/eth/network_mod/comp/network_mod_core/comps/ftile/ftile_2x100g4.vhd‎

Lines changed: 16 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -497,12 +497,13 @@ begin
497497
STATE => open -- debug purposes only. Can be left open in the future
498498
);
499499

500-
end generate;
500+
mi_ardy_phy(IA_INDEX) <= not reconfig_waitrequest(IA_INDEX) and not init_busy;
501501

502-
mi_ardy_conversion_g: for i in PMA_LANES downto 0 generate
503-
mi_ardy_phy(i) <= not reconfig_waitrequest(i);
504502
end generate;
505503

504+
mi_ardy_phy(0) <= not reconfig_waitrequest(0);
505+
506+
506507
CLK_ETH_OUT <= ftile_clk_out;
507508

508509
-- =========================================================================
@@ -548,37 +549,37 @@ begin
548549
i_reconfig_xcvr0_addr => reconfig_addr (1)(18-1 downto 0),
549550
i_reconfig_xcvr0_byteenable => (others => '1'), -- not supported in MI IA yet
550551
o_reconfig_xcvr0_readdata_valid => reconfig_readdata_valid (1),
551-
i_reconfig_xcvr0_read => reconfig_read_drp (1),
552-
i_reconfig_xcvr0_write => reconfig_write_drp (1),
552+
i_reconfig_xcvr0_read => reconfig_read (1),
553+
i_reconfig_xcvr0_write => reconfig_write (1),
553554
o_reconfig_xcvr0_readdata => reconfig_readdata (1),
554-
i_reconfig_xcvr0_writedata => reconfig_writedata_drp (1),
555+
i_reconfig_xcvr0_writedata => reconfig_writedata (1),
555556
o_reconfig_xcvr0_waitrequest => reconfig_waitrequest (1),
556557
-- XCVR reconfig inf (0x2)
557558
i_reconfig_xcvr1_addr => reconfig_addr (2)(18-1 downto 0),
558559
i_reconfig_xcvr1_byteenable => (others => '1'), -- not supported in MI IA yet
559560
o_reconfig_xcvr1_readdata_valid => reconfig_readdata_valid (2),
560-
i_reconfig_xcvr1_read => reconfig_read_drp (2),
561-
i_reconfig_xcvr1_write => reconfig_write_drp (2),
561+
i_reconfig_xcvr1_read => reconfig_read (2),
562+
i_reconfig_xcvr1_write => reconfig_write (2),
562563
o_reconfig_xcvr1_readdata => reconfig_readdata (2),
563-
i_reconfig_xcvr1_writedata => reconfig_writedata_drp (2),
564+
i_reconfig_xcvr1_writedata => reconfig_writedata (2),
564565
o_reconfig_xcvr1_waitrequest => reconfig_waitrequest (2),
565566
-- XCVR reconfig inf (0x3)
566567
i_reconfig_xcvr2_addr => reconfig_addr (3)(18-1 downto 0),
567568
i_reconfig_xcvr2_byteenable => (others => '1'), -- not supported in MI IA yet
568569
o_reconfig_xcvr2_readdata_valid => reconfig_readdata_valid (3),
569-
i_reconfig_xcvr2_read => reconfig_read_drp (3),
570-
i_reconfig_xcvr2_write => reconfig_write_drp (3),
570+
i_reconfig_xcvr2_read => reconfig_read (3),
571+
i_reconfig_xcvr2_write => reconfig_write (3),
571572
o_reconfig_xcvr2_readdata => reconfig_readdata (3),
572-
i_reconfig_xcvr2_writedata => reconfig_writedata_drp (3),
573+
i_reconfig_xcvr2_writedata => reconfig_writedata (3),
573574
o_reconfig_xcvr2_waitrequest => reconfig_waitrequest (3),
574575
-- XCVR reconfig inf (0x4)
575576
i_reconfig_xcvr3_addr => reconfig_addr (4)(18-1 downto 0),
576577
i_reconfig_xcvr3_byteenable => (others => '1'), -- not supported in MI IA yet
577578
o_reconfig_xcvr3_readdata_valid => reconfig_readdata_valid (4),
578-
i_reconfig_xcvr3_read => reconfig_read_drp (4),
579-
i_reconfig_xcvr3_write => reconfig_write_drp (4),
579+
i_reconfig_xcvr3_read => reconfig_read (4),
580+
i_reconfig_xcvr3_write => reconfig_write (4),
580581
o_reconfig_xcvr3_readdata => reconfig_readdata (4),
581-
i_reconfig_xcvr3_writedata => reconfig_writedata_drp (4),
582+
i_reconfig_xcvr3_writedata => reconfig_writedata (4),
582583
o_reconfig_xcvr3_waitrequest => reconfig_waitrequest (4),
583584
-- MAC data
584585
o_rx_block_lock => ftile_rx_block_lock,

‎core/comp/eth/network_mod/comp/network_mod_core/comps/ftile/ftile_2x200g4.vhd‎

Lines changed: 15 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -494,12 +494,12 @@ begin
494494
STATE => open -- debug purposes only. Can be left open in the future
495495
);
496496

497-
end generate;
497+
mi_ardy_phy(IA_INDEX) <= not reconfig_waitrequest(IA_INDEX) and not init_busy;
498498

499-
mi_ardy_conversion_g: for i in PMA_LANES downto 0 generate
500-
mi_ardy_phy(i) <= not reconfig_waitrequest(i);
501499
end generate;
502500

501+
mi_ardy_phy(0) <= not reconfig_waitrequest(0);
502+
503503
CLK_ETH_OUT <= ftile_clk_out;
504504

505505
-- =========================================================================
@@ -545,37 +545,37 @@ begin
545545
i_reconfig_xcvr0_addr => reconfig_addr (1)(18-1 downto 0),
546546
i_reconfig_xcvr0_byteenable => (others => '1'), -- not supported in MI IA yet
547547
o_reconfig_xcvr0_readdata_valid => reconfig_readdata_valid (1),
548-
i_reconfig_xcvr0_read => reconfig_read_drp (1),
549-
i_reconfig_xcvr0_write => reconfig_write_drp (1),
548+
i_reconfig_xcvr0_read => reconfig_read (1),
549+
i_reconfig_xcvr0_write => reconfig_write (1),
550550
o_reconfig_xcvr0_readdata => reconfig_readdata (1),
551-
i_reconfig_xcvr0_writedata => reconfig_writedata_drp (1),
551+
i_reconfig_xcvr0_writedata => reconfig_writedata (1),
552552
o_reconfig_xcvr0_waitrequest => reconfig_waitrequest (1),
553553
-- XCVR reconfig inf (0x2)
554554
i_reconfig_xcvr1_addr => reconfig_addr (2)(18-1 downto 0),
555555
i_reconfig_xcvr1_byteenable => (others => '1'), -- not supported in MI IA yet
556556
o_reconfig_xcvr1_readdata_valid => reconfig_readdata_valid (2),
557-
i_reconfig_xcvr1_read => reconfig_read_drp (2),
558-
i_reconfig_xcvr1_write => reconfig_write_drp (2),
557+
i_reconfig_xcvr1_read => reconfig_read (2),
558+
i_reconfig_xcvr1_write => reconfig_write (2),
559559
o_reconfig_xcvr1_readdata => reconfig_readdata (2),
560-
i_reconfig_xcvr1_writedata => reconfig_writedata_drp (2),
560+
i_reconfig_xcvr1_writedata => reconfig_writedata (2),
561561
o_reconfig_xcvr1_waitrequest => reconfig_waitrequest (2),
562562
-- XCVR reconfig inf (0x3)
563563
i_reconfig_xcvr2_addr => reconfig_addr (3)(18-1 downto 0),
564564
i_reconfig_xcvr2_byteenable => (others => '1'), -- not supported in MI IA yet
565565
o_reconfig_xcvr2_readdata_valid => reconfig_readdata_valid (3),
566-
i_reconfig_xcvr2_read => reconfig_read_drp (3),
567-
i_reconfig_xcvr2_write => reconfig_write_drp (3),
566+
i_reconfig_xcvr2_read => reconfig_read (3),
567+
i_reconfig_xcvr2_write => reconfig_write (3),
568568
o_reconfig_xcvr2_readdata => reconfig_readdata (3),
569-
i_reconfig_xcvr2_writedata => reconfig_writedata_drp (3),
569+
i_reconfig_xcvr2_writedata => reconfig_writedata (3),
570570
o_reconfig_xcvr2_waitrequest => reconfig_waitrequest (3),
571571
-- XCVR reconfig inf (0x4)
572572
i_reconfig_xcvr3_addr => reconfig_addr (4)(18-1 downto 0),
573573
i_reconfig_xcvr3_byteenable => (others => '1'), -- not supported in MI IA yet
574574
o_reconfig_xcvr3_readdata_valid => reconfig_readdata_valid (4),
575-
i_reconfig_xcvr3_read => reconfig_read_drp (4),
576-
i_reconfig_xcvr3_write => reconfig_write_drp (4),
575+
i_reconfig_xcvr3_read => reconfig_read (4),
576+
i_reconfig_xcvr3_write => reconfig_write (4),
577577
o_reconfig_xcvr3_readdata => reconfig_readdata (4),
578-
i_reconfig_xcvr3_writedata => reconfig_writedata_drp (4),
578+
i_reconfig_xcvr3_writedata => reconfig_writedata (4),
579579
o_reconfig_xcvr3_waitrequest => reconfig_waitrequest (4),
580580
-- MAC data
581581
o_rx_block_lock => ftile_rx_block_lock,

‎core/comp/eth/network_mod/comp/network_mod_core/comps/ftile/ftile_2x40g4.vhd‎

Lines changed: 15 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -495,12 +495,12 @@ begin
495495
STATE => open -- debug purposes only. Can be left open in the future
496496
);
497497

498-
end generate;
498+
mi_ardy_phy(IA_INDEX) <= not reconfig_waitrequest(IA_INDEX) and not init_busy;
499499

500-
mi_ardy_conversion_g: for i in PMA_LANES downto 0 generate
501-
mi_ardy_phy(i) <= not reconfig_waitrequest(i);
502500
end generate;
503501

502+
mi_ardy_phy(0) <= not reconfig_waitrequest(0);
503+
504504
CLK_ETH_OUT <= ftile_clk_out;
505505

506506
-- =========================================================================
@@ -546,37 +546,37 @@ begin
546546
i_reconfig_xcvr0_addr => reconfig_addr (1)(18-1 downto 0),
547547
i_reconfig_xcvr0_byteenable => (others => '1'), -- not supported in MI IA yet
548548
o_reconfig_xcvr0_readdata_valid => reconfig_readdata_valid (1),
549-
i_reconfig_xcvr0_read => reconfig_read_drp (1),
550-
i_reconfig_xcvr0_write => reconfig_write_drp (1),
549+
i_reconfig_xcvr0_read => reconfig_read (1),
550+
i_reconfig_xcvr0_write => reconfig_write (1),
551551
o_reconfig_xcvr0_readdata => reconfig_readdata (1),
552-
i_reconfig_xcvr0_writedata => reconfig_writedata_drp (1),
552+
i_reconfig_xcvr0_writedata => reconfig_writedata (1),
553553
o_reconfig_xcvr0_waitrequest => reconfig_waitrequest (1),
554554
-- XCVR(1) reconfig inf (0x2)
555555
i_reconfig_xcvr1_addr => reconfig_addr (2)(18-1 downto 0),
556556
i_reconfig_xcvr1_byteenable => (others => '1'), -- not supported in MI IA yet
557557
o_reconfig_xcvr1_readdata_valid => reconfig_readdata_valid (2),
558-
i_reconfig_xcvr1_read => reconfig_read_drp (2),
559-
i_reconfig_xcvr1_write => reconfig_write_drp (2),
558+
i_reconfig_xcvr1_read => reconfig_read (2),
559+
i_reconfig_xcvr1_write => reconfig_write (2),
560560
o_reconfig_xcvr1_readdata => reconfig_readdata (2),
561-
i_reconfig_xcvr1_writedata => reconfig_writedata_drp (2),
561+
i_reconfig_xcvr1_writedata => reconfig_writedata (2),
562562
o_reconfig_xcvr1_waitrequest => reconfig_waitrequest (2),
563563
-- XCVR(2) reconfig inf (0x3)
564564
i_reconfig_xcvr2_addr => reconfig_addr (3)(18-1 downto 0),
565565
i_reconfig_xcvr2_byteenable => (others => '1'), -- not supported in MI IA yet
566566
o_reconfig_xcvr2_readdata_valid => reconfig_readdata_valid (3),
567-
i_reconfig_xcvr2_read => reconfig_read_drp (3),
568-
i_reconfig_xcvr2_write => reconfig_write_drp (3),
567+
i_reconfig_xcvr2_read => reconfig_read (3),
568+
i_reconfig_xcvr2_write => reconfig_write (3),
569569
o_reconfig_xcvr2_readdata => reconfig_readdata (3),
570-
i_reconfig_xcvr2_writedata => reconfig_writedata_drp (3),
570+
i_reconfig_xcvr2_writedata => reconfig_writedata (3),
571571
o_reconfig_xcvr2_waitrequest => reconfig_waitrequest (3),
572572
-- XCVR(3) reconfig inf (0x4)
573573
i_reconfig_xcvr3_addr => reconfig_addr (4)(18-1 downto 0),
574574
i_reconfig_xcvr3_byteenable => (others => '1'), -- not supported in MI IA yet
575575
o_reconfig_xcvr3_readdata_valid => reconfig_readdata_valid (4),
576-
i_reconfig_xcvr3_read => reconfig_read_drp (4),
577-
i_reconfig_xcvr3_write => reconfig_write_drp (4),
576+
i_reconfig_xcvr3_read => reconfig_read (4),
577+
i_reconfig_xcvr3_write => reconfig_write (4),
578578
o_reconfig_xcvr3_readdata => reconfig_readdata (4),
579-
i_reconfig_xcvr3_writedata => reconfig_writedata_drp (4),
579+
i_reconfig_xcvr3_writedata => reconfig_writedata (4),
580580
o_reconfig_xcvr3_waitrequest => reconfig_waitrequest (4),
581581
-- MAC data
582582
o_rx_block_lock => ftile_rx_block_lock,

‎core/comp/eth/network_mod/comp/network_mod_core/comps/ftile/ftile_4x100g2.vhd‎

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -478,12 +478,12 @@ begin
478478
STATE => open -- debug purposes only. Can be left open in the future
479479
);
480480

481-
end generate;
481+
mi_ardy_phy(IA_INDEX) <= not reconfig_waitrequest(IA_INDEX) and not init_busy;
482482

483-
mi_ardy_conversion_g: for i in PMA_LANES downto 0 generate
484-
mi_ardy_phy(i) <= not reconfig_waitrequest(i);
485483
end generate;
486484

485+
mi_ardy_phy(0) <= not reconfig_waitrequest(0);
486+
487487
CLK_ETH_OUT <= ftile_clk_out;
488488

489489
-- =========================================================================
@@ -529,19 +529,19 @@ begin
529529
i_reconfig_xcvr0_addr => reconfig_addr (1)(18-1 downto 0),
530530
i_reconfig_xcvr0_byteenable => (others => '1'), -- not supported in MI IA yet
531531
o_reconfig_xcvr0_readdata_valid => reconfig_readdata_valid (1),
532-
i_reconfig_xcvr0_read => reconfig_read_drp (1),
533-
i_reconfig_xcvr0_write => reconfig_write_drp (1),
532+
i_reconfig_xcvr0_read => reconfig_read (1),
533+
i_reconfig_xcvr0_write => reconfig_write (1),
534534
o_reconfig_xcvr0_readdata => reconfig_readdata (1),
535-
i_reconfig_xcvr0_writedata => reconfig_writedata_drp (1),
535+
i_reconfig_xcvr0_writedata => reconfig_writedata (1),
536536
o_reconfig_xcvr0_waitrequest => reconfig_waitrequest (1),
537537
-- XCVR reconfig inf (0x2)
538538
i_reconfig_xcvr1_addr => reconfig_addr (2)(18-1 downto 0),
539539
i_reconfig_xcvr1_byteenable => (others => '1'), -- not supported in MI IA yet
540540
o_reconfig_xcvr1_readdata_valid => reconfig_readdata_valid (2),
541-
i_reconfig_xcvr1_read => reconfig_read_drp (2),
542-
i_reconfig_xcvr1_write => reconfig_write_drp (2),
541+
i_reconfig_xcvr1_read => reconfig_read (2),
542+
i_reconfig_xcvr1_write => reconfig_write (2),
543543
o_reconfig_xcvr1_readdata => reconfig_readdata (2),
544-
i_reconfig_xcvr1_writedata => reconfig_writedata_drp (2),
544+
i_reconfig_xcvr1_writedata => reconfig_writedata (2),
545545
o_reconfig_xcvr1_waitrequest => reconfig_waitrequest (2),
546546
-- MAC data
547547
o_rx_block_lock => ftile_rx_block_lock,

‎core/comp/eth/network_mod/comp/network_mod_core/comps/ftile/ftile_8x10g1.vhd‎

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -466,12 +466,13 @@ begin
466466
WAITREQUEST => reconfig_waitrequest(IA_INDEX),
467467
STATE => open -- debug purposes only. Can be left open in the future
468468
);
469-
end generate;
470469

471-
mi_ardy_conversion_g: for i in PMA_LANES downto 0 generate
472-
mi_ardy_phy(i) <= not reconfig_waitrequest(i);
470+
mi_ardy_phy(IA_INDEX) <= not reconfig_waitrequest(IA_INDEX) and not init_busy;
471+
473472
end generate;
474473

474+
mi_ardy_phy(0) <= not reconfig_waitrequest(0);
475+
475476
CLK_ETH_OUT <= ftile_clk_out;
476477

477478
-- =========================================================================

‎core/comp/eth/network_mod/comp/network_mod_core/comps/ftile/ftile_8x25g1.vhd‎

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -469,12 +469,13 @@ begin
469469
WAITREQUEST => reconfig_waitrequest(IA_INDEX),
470470
STATE => open -- debug purposes only. Can be left open in the future
471471
);
472-
end generate;
473472

474-
mi_ardy_conversion_g: for i in PMA_LANES downto 0 generate
475-
mi_ardy_phy(i) <= not reconfig_waitrequest(i);
473+
mi_ardy_phy(IA_INDEX) <= not reconfig_waitrequest(IA_INDEX) and not init_busy;
474+
476475
end generate;
477476

477+
mi_ardy_phy(0) <= not reconfig_waitrequest(0);
478+
478479
CLK_ETH_OUT <= ftile_clk_out;
479480

480481
-- =========================================================================

‎core/comp/eth/network_mod/comp/network_mod_core/comps/ftile/ftile_8x50g1.vhd‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -470,12 +470,12 @@ begin
470470
STATE => open -- debug purposes only. Can be left open in the future
471471
);
472472

473-
end generate;
473+
mi_ardy_phy(IA_INDEX) <= not reconfig_waitrequest(IA_INDEX) and not init_busy;
474474

475-
mi_ardy_conversion_g: for i in PMA_LANES downto 0 generate
476-
mi_ardy_phy(i) <= not reconfig_waitrequest(i);
477475
end generate;
478476

477+
mi_ardy_phy(0) <= not reconfig_waitrequest(0);
478+
479479
CLK_ETH_OUT <= ftile_clk_out;
480480

481481
-- =========================================================================
@@ -521,10 +521,10 @@ begin
521521
i_reconfig_xcvr0_addr => reconfig_addr (1)(18-1 downto 0),
522522
i_reconfig_xcvr0_byteenable => (others => '1'), -- not supported in MI IA yet
523523
o_reconfig_xcvr0_readdata_valid => reconfig_readdata_valid (1),
524-
i_reconfig_xcvr0_read => reconfig_read_drp (1),
525-
i_reconfig_xcvr0_write => reconfig_write_drp (1),
524+
i_reconfig_xcvr0_read => reconfig_read (1),
525+
i_reconfig_xcvr0_write => reconfig_write (1),
526526
o_reconfig_xcvr0_readdata => reconfig_readdata (1),
527-
i_reconfig_xcvr0_writedata => reconfig_writedata_drp (1),
527+
i_reconfig_xcvr0_writedata => reconfig_writedata (1),
528528
o_reconfig_xcvr0_waitrequest => reconfig_waitrequest (1),
529529
-- MAC data
530530
o_rx_block_lock => ftile_rx_block_lock,

‎core/comp/eth/network_mod/comp/network_mod_core/comps/ftile/ftile_multirate_eth_2x100g4.vhd‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -645,12 +645,12 @@ begin
645645
STATE => open -- debug purposes only. Can be left open in the future
646646
);
647647

648-
end generate;
648+
reconfig_waitrequest_drp(IA_INDEX) <= not reconfig_waitrequest(IA_INDEX) and not init_busy;
649649

650-
mi_ardy_conversion_g: for i in PMA_LANES downto 0 generate
651-
reconfig_waitrequest_drp(i) <= not reconfig_waitrequest(i);
652650
end generate;
653651

652+
reconfig_waitrequest_drp(0) <= not reconfig_waitrequest(0);
653+
654654
CLK_ETH_OUT <= ftile_clk_out;
655655
-- =========================================================================
656656
-- DR_CTRL

‎core/comp/eth/network_mod/comp/network_mod_core/comps/ftile/ftile_multirate_eth_8x25g1_8x10g1.vhd‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -516,12 +516,12 @@ begin
516516
STATE => open -- debug purposes only. Can be left open in the future
517517
);
518518

519-
end generate;
519+
reconfig_waitrequest_drp(IA_INDEX) <= not reconfig_waitrequest(IA_INDEX) and not init_busy;
520520

521-
mi_ardy_conversion_g: for i in PMA_LANES downto 0 generate
522-
reconfig_waitrequest_drp(i) <= not reconfig_waitrequest(i);
523521
end generate;
524522

523+
reconfig_waitrequest_drp(0) <= not reconfig_waitrequest(0);
524+
525525
CLK_ETH_OUT <= ftile_clk_out;
526526
-- =========================================================================
527527
-- DR_CTRL

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